https://lore.kernel.org/all/20240409120108.2303d...@canb.auug.org.au/
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 8
drivers/gpu/drm/msm/Makefile| 9 -
drivers/gpu/drm/msm/registers/gen_header.py | 14 +++---
3 files change
: linux-ker...@vger.kernel.org
Signed-off-by: Dmitry Baryshkov
Changes in v2:
- added validation of XML files agains schema in in DRM CI
- Link to v1:
https://lore.kernel.org/r/20240409-fd-fix-lxml-v1-1-e5c300d6c...@linaro.org
---
Dmitry Baryshkov (2):
drm/msm/gen_header: allow skipping the
sertions(+)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 88
> -
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> 2 files changed, 89 insertions(+), 1 deletion(-)
>
I didn't check the register bits, but the rest looks fine
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
-
> 1 file changed, 25 insertions(+), 3 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
+++
> include/linux/firmware/qcom/qcom_scm.h | 23 +++
> 3 files changed, 40 insertions(+)
>
With the commit message improved:
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Fri, 26 Apr 2024 at 18:36, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 4:24 PM Dmitry Baryshkov
> wrote:
> >
> > On Fri, 26 Apr 2024 at 18:08, Connor Abbott wrote:
> > >
> > > On Fri, Apr 26, 2024 at 3:53 PM Dmitry Baryshkov
> > > wro
On Fri, 26 Apr 2024 at 18:08, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 3:53 PM Dmitry Baryshkov
> wrote:
> >
> > On Fri, 26 Apr 2024 at 17:05, Connor Abbott wrote:
> > >
> > > On Fri, Apr 26, 2024 at 2:31 PM Dmitry Baryshkov
> > > wro
On Fri, 26 Apr 2024 at 17:05, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 2:31 PM Dmitry Baryshkov
> wrote:
> >
> > On Fri, 26 Apr 2024 at 15:35, Connor Abbott wrote:
> > >
> > > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > > wro
On Fri, 26 Apr 2024 at 15:54, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 1:35 PM Connor Abbott wrote:
> >
> > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > wrote:
> > >
> > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> >
On Fri, 26 Apr 2024 at 15:35, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> wrote:
> >
> > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> > >
> > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a metho
On Fri, 26 Apr 2024 at 15:46, Rob Clark wrote:
>
> On Thu, Apr 25, 2024 at 4:02 PM Dmitry Baryshkov
> wrote:
> >
> > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> > >
> > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
sertions(+)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
>
> On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> initialize cx_mem. Copy this from downstream (minus BCL which we
> currently don't support). On a750, this includes a new "fuse" register
> which can be used by qcom_scm
On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
>
> On a750, Qualcomm decided to gate support for certain features behind a
> "software fuse." This consists of a register in the cx_mem zone, which
> is normally only writeable by the TrustZone firmware. On bootup it is
> 0, and we must call an
On Wed, 24 Apr 2024 at 15:21, Connor Abbott wrote:
>
> On Mon, Apr 1, 2024 at 3:52 AM Dmitry Baryshkov
> wrote:
> >
> > Import Adreno registers database for A6xx from the Mesa, commit
> > 639488f924d9 ("freedreno/registers: limit the rules schema").
&g
y/dsi_phy_14nm.c | 3 +-
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 81
> +++---
> 3 files changed, 54 insertions(+), 33 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
dsi/phy/dsi_phy_28nm_8960.c | 205 +++
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 320
>
> 7 files changed, 645 insertions(+), 703 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Mon, Apr 22, 2024 at 11:17:15AM -0700, Abhinav Kumar wrote:
>
>
> On 4/19/2024 7:33 PM, Dmitry Baryshkov wrote:
> > Since commit 3c74682637e6 ("drm/msm/mdp4: move resource allocation to
> > the _probe function") the mdp4_kms data is allocated during probe. I
On Mon, Apr 22, 2024 at 09:12:20AM -0700, Abhinav Kumar wrote:
>
>
> On 4/21/2024 3:35 PM, Dmitry Baryshkov wrote:
> > On Sat, Apr 20, 2024 at 04:02:00PM -0700, Abhinav Kumar wrote:
> > >
> > >
> > > On 4/19/2024 7:33 PM, Dmitry Baryshkov wrot
On Mon, Apr 22, 2024 at 10:23:18AM -0700, Abhinav Kumar wrote:
>
>
> On 4/21/2024 3:35 PM, Dmitry Baryshkov wrote:
> > On Sat, Apr 20, 2024 at 04:02:00PM -0700, Abhinav Kumar wrote:
> > >
> > >
> > > On 4/19/2024 7:33 PM, Dmitry Baryshkov wrot
ni Nikula
> Cc: Rodrigo Vivi
> Cc: Joonas Lahtinen
> Cc: Tvrtko Ursulin
> Cc: Frank Binns
> Cc: Matt Coster
> Cc: Rob Clark
> Cc: Abhinav Kumar
> Cc: Dmitry Baryshkov
> Cc: Sean Paul
> Cc: Marijn Suijten
> Cc: Karol Herbst
> Cc: Lyude Paul
> Cc: Danil
On Fri, Apr 19, 2024 at 07:37:44PM -0700, Abhinav Kumar wrote:
>
>
> On 4/19/2024 6:34 PM, Dmitry Baryshkov wrote:
> > On Fri, Apr 19, 2024 at 05:14:01PM -0700, Abhinav Kumar wrote:
> > >
> > >
> > > On 3/19/2024 6:22 AM, Dmit
On Fri, Apr 19, 2024 at 07:32:35PM -0700, Abhinav Kumar wrote:
>
>
> On 4/19/2024 6:26 PM, Dmitry Baryshkov wrote:
> > On Fri, Apr 19, 2024 at 04:43:20PM -0700, Abhinav Kumar wrote:
> > >
> > >
> > > On 3/19/2024 6:21 AM, Dmitry Baryshkov wrote:
> &
On Sat, Apr 20, 2024 at 04:02:00PM -0700, Abhinav Kumar wrote:
>
>
> On 4/19/2024 7:33 PM, Dmitry Baryshkov wrote:
> > MSM display drivers provide kms structure allocated during probe().
> > Don't clean up priv->kms field in case of an error. Otherwise probe
>
Now as all subdrivers were converted to use common database of formats,
drop the get_format() callback and use mdp_get_format() directly.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1
Structures dpu_format and mdp_format are largely the same structures.
In order to remove duplication between format databases, merge these two
stucture definitions into the global struct msm_format.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1
Finally remove duplication between DPU and generic MDP code by merging
DPU format lists to the MDP format database.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 7 +-
drivers/gpu/drm/msm
Instead of having a u8 or bool field unpack_align_msb, convert it to the
flag, this save space in the tables and allows us to handle all booleans
in the same way.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 12
Instead of having a u8 or bool field unpack_tight, convert it to the
flag, this save space in the tables and allows us to handle all booleans
in the same way.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 22
drivers
In preparation to merger of formats databases, pull format flag
definitions to mdp_format.h header, so that they are visibile to both
dpu and mdp drivers.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 98 ++---
drivers/gpu/drm/msm/disp
Using bitmap for the flags results in a clumsy syntax on test_bit,
replace it with unsigned long type and simple binary ops.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 18 +-
drivers/gpu/drm/msm/disp/dpu1
-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 57 +++---
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 36 ++-
drivers/gpu/drm/msm/disp/mdp_format.c | 28 ---
drivers/gpu/drm/msm/disp/mdp_kms.h | 1 -
4
Instead of having DPU-specific defines, switch to the definitions from
the mdp_common.xml.h file. This is the preparation for merged of DPU and
MDP format tables.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 8 +-
.../gpu
d all formats data to the new header mdp_formats.h (Abhinav)
- Dropped the alpha_enable flag changes (Abhinav)
- Link to v1:
https://lore.kernel.org/r/20231202214016.1257621-1-dmitry.barysh...@linaro.org
---
Dmitry Baryshkov (9):
drm/msm/dpu: use format-related definitions from mdp_common.
On Sat, 20 Apr 2024 at 06:05, Abhinav Kumar wrote:
>
>
>
> On 3/19/2024 6:22 AM, Dmitry Baryshkov wrote:
> > Lift mode_config limits set by the DPU driver to the actual FB limits as
> > handled by the dpu_plane.c.
> >
> > Signed-off-by: Dmitry Baryshkov
&g
probe
deferral.
Fixes: 3c74682637e6 ("drm/msm/mdp4: move resource allocation to the _probe
function")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 28 +---
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm
MSM display drivers provide kms structure allocated during probe().
Don't clean up priv->kms field in case of an error. Otherwise probe
functions might fail after KMS probe deferral.
Fixes: a2ab5d5bb6b1 ("drm/msm: allow passing struct msm_kms to msm_drv_probe()")
Signed-off-by
Correct c&p error from the conversion of LCDC regulators to the bulk
API.
Fixes: 54f1fbcb47d4 ("drm/msm/mdp4: use bulk regulators API for LCDC encoder")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 2 +-
1 file changed, 1 insertion(
While testing MDP4 LVDS support I noticed several issues (two are
related to probe deferral case and last one is a c&p error in LCDC
part). Fix those issues.
Signed-off-by: Dmitry Baryshkov
---
Dmitry Baryshkov (3):
drm/msm: don't clean up priv->kms prematurely
drm/msm
On Fri, Apr 19, 2024 at 05:16:30PM -0700, Abhinav Kumar wrote:
>
>
> On 3/19/2024 6:22 AM, Dmitry Baryshkov wrote:
> > Check that the plane pitch doesn't overflow the maximum pitch size
> > allowed by the hardware.
> >
> > Signed-off-by: Dmitry Baryshkov
On Fri, Apr 19, 2024 at 05:14:01PM -0700, Abhinav Kumar wrote:
>
>
> On 3/19/2024 6:22 AM, Dmitry Baryshkov wrote:
> > Move a call to dpu_format_populate_plane_sizes() to the atomic_check
> > step, so that any issues with the FB layout can be reported as early as
> >
On Fri, Apr 19, 2024 at 04:43:20PM -0700, Abhinav Kumar wrote:
>
>
> On 3/19/2024 6:21 AM, Dmitry Baryshkov wrote:
> > The msm_kms_funcs::check_modified_format() callback is not used by the
> > driver. Drop it completely.
> >
> > Signed-off-by: Dmitry Baryshk
On Sat, Apr 20, 2024 at 12:18:39AM +0200, Marijn Suijten wrote:
> On 2024-04-17 14:58:25, Dmitry Baryshkov wrote:
> > On Wed, 17 Apr 2024 at 02:57, Marijn Suijten
> > wrote:
> > >
> > > When configuring the timing of DSI hosts (interfaces) in
> > >
On Sat, 20 Apr 2024 at 00:06, Abhinav Kumar wrote:
>
>
>
> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> > MDP4 and MDP5 drivers enumerate supported formats each time the plane is
> > created. In preparation to merger of MDP DPU format databases, define
> > precise
Early python 3 versions do not support the 'required' argument for
> the argparse add_subparsers().
>
> Fix both of the above so that older versions of python 3 still work.
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Thu, 18 Apr 2024 at 14:31, Konrad Dybcio wrote:
>
> On 18.04.2024 1:07 PM, Dmitry Baryshkov wrote:
> > On Thu, Apr 18, 2024 at 11:51:16AM +0200, Konrad Dybcio wrote:
> >> On 18.04.2024 1:43 AM, Dmitry Baryshkov wrote:
> >>> On Wed, Apr 17, 2024 at 10:0
On Thu, Apr 18, 2024 at 11:57:35AM +0200, Konrad Dybcio wrote:
> On 18.04.2024 1:49 AM, Dmitry Baryshkov wrote:
> > On Wed, Apr 17, 2024 at 10:02:58PM +0200, Konrad Dybcio wrote:
> >> There is no need to reinvent the wheel for simple read-match-set logic.
> >>
>
On Thu, Apr 18, 2024 at 11:51:16AM +0200, Konrad Dybcio wrote:
> On 18.04.2024 1:43 AM, Dmitry Baryshkov wrote:
> > On Wed, Apr 17, 2024 at 10:02:55PM +0200, Konrad Dybcio wrote:
> >> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
> >> abstracted thr
On Thu, Apr 18, 2024 at 11:53:31AM +0200, Konrad Dybcio wrote:
> On 18.04.2024 1:39 AM, Dmitry Baryshkov wrote:
> > On Wed, Apr 17, 2024 at 10:02:54PM +0200, Konrad Dybcio wrote:
> >> Recent (SM8550+ ish) Qualcomm SoCs have a new mechanism for precisely
> >> identifyi
gt; arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 -
> 1 file changed, 20 insertions(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Wed, Apr 17, 2024 at 10:02:58PM +0200, Konrad Dybcio wrote:
> There is no need to reinvent the wheel for simple read-match-set logic.
>
> Make speedbin discovery and assignment generation independent.
>
> This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx,
> which has no represe
On Wed, Apr 17, 2024 at 10:02:57PM +0200, Konrad Dybcio wrote:
> In preparation for commonizing the speedbin handling code.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 6 ++
> 1 file changed, 6 insertions(+)
Reviewed-by: Dmitry Ba
On Wed, Apr 17, 2024 at 10:02:56PM +0200, Konrad Dybcio wrote:
> Add speebin data for A740, as found on SM8550 and derivative SoCs.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 5 +
> 1 file changed, 5 insertions(+)
>
Reviewed
On Wed, Apr 17, 2024 at 10:02:55PM +0200, Konrad Dybcio wrote:
> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
> abstracted through SMEM, instead of being directly available in a fuse.
>
> Add support for SMEM-based speed binning, which includes getting
> "feature code" and "
On Wed, Apr 17, 2024 at 10:02:54PM +0200, Konrad Dybcio wrote:
> Recent (SM8550+ ish) Qualcomm SoCs have a new mechanism for precisely
> identifying the specific SKU and the precise speed bin (in the general
> meaning of this word, anyway): a pair of values called Product Code
> and Feature Code.
>
I really have mixed feelings towards such patches. On one hand it
improves readability, on the other hand, it's just a name, it has no
specific value.
Still:
Reviewed-by: Dmitry Baryshkov
>
> Signed-off-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 14
On Wed, Apr 17, 2024 at 01:57:45AM +0200, Marijn Suijten wrote:
> This comment one line down references a single, "same CTL" that controls
> two interfaces, so the comment should clearly describe two interfaces
> used with a single active CTL and not "two CTLs".
>
> Fixes: 25fdd5933e4c ("drm/msm:
gt; other blocks and ACTIVE bitmasks), leaving the rest enabled.
>
> Fixes: 77f6da90487c ("drm/msm/disp/dpu1: Add DSC support in hw_ctl")
> Signed-off-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
rt")
> Signed-off-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 ---
> 1 file changed, 3 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
hat up like hdisplay here.
>
> Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
> Signed-off-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
ot;drm/msm/dsi: adjust dsi timing for dual dsi mode")
> Signed-off-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Wed, 17 Apr 2024 at 02:57, Marijn Suijten
wrote:
>
> Ordering issues here cause an uninitalized (default STANDALONE)
> usecase to be programmed (which appears to be a MUX) in some cases
> when msm_dsi_host_register() is called, leading to the slave PLL in
> bonded-DSI mode to source from a cloc
On Fri, 12 Apr 2024 at 22:47, Abhinav Kumar wrote:
>
>
>
> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> > Finally remove duplication between DPU and generic MDP code by merging
> > DPU format lists to the MDP format database.
> >
> > Signed-off-by: Dmitry
On Fri, 12 Apr 2024 at 19:15, Jon Hunter wrote:
>
> Hi Dmitry,
>
> On 01/04/2024 03:42, Dmitry Baryshkov wrote:
> > Generate DRM/MSM headers on the fly during kernel build. This removes a
> > need to push register changes to Mesa with the following manual
> >
On Fri, 12 Apr 2024 at 00:35, Konrad Dybcio wrote:
>
>
>
> On 4/10/24 21:26, Dmitry Baryshkov wrote:
> > On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 4/6/24 05:23, Dmitry Baryshkov wrote:
> >>> On F
On Fri, 12 Apr 2024 at 00:20, Abhinav Kumar wrote:
>
>
>
> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> > Instead of having a bool field alpha_enable, convert it to the
> > flag, this save space in the tables and allows us to handle all booleans
> > in the s
On Thu, Apr 11, 2024 at 08:27:22AM -0700, Bjorn Andersson wrote:
> On Thu, Apr 11, 2024 at 04:31:41AM +0300, Dmitry Baryshkov wrote:
> > On Wed, Apr 10, 2024 at 11:52:52PM +0200, Konrad Dybcio wrote:
> [..]
> > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> >
On Thu, 11 Apr 2024 at 22:15, Abhinav Kumar wrote:
>
>
>
> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> > Structures dpu_format and mdp_format are largely the same structures.
> > In order to remove duplication between format databases, merge these two
> > stuctu
On Thu, 11 Apr 2024 at 02:54, Abhinav Kumar wrote:
>
>
>
> On 4/10/2024 2:12 PM, Dmitry Baryshkov wrote:
> > On Wed, Apr 10, 2024 at 01:18:42PM -0700, Abhinav Kumar wrote:
> >>
> >>
> >> On 4/10/2024 1:16 PM, Dmitry Baryshkov wrote:
> >>>
On Wed, Apr 10, 2024 at 11:52:52PM +0200, Konrad Dybcio wrote:
> Totally useless.
>
> Signed-off-by: Konrad Dybcio
> ---
> only compile-tested
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 12 ++--
> drivers/gpu/drm/msm/adren
On Thu, 11 Apr 2024 at 04:20, Dmitry Baryshkov
wrote:
>
> On Thu, 11 Apr 2024 at 02:54, Abhinav Kumar wrote:
> >
> >
> >
> > On 4/10/2024 2:12 PM, Dmitry Baryshkov wrote:
> > > On Wed, Apr 10, 2024 at 01:18:42PM -0700, Abhinav Kumar wrote:
> >
On Thu, 11 Apr 2024 at 02:54, Abhinav Kumar wrote:
>
>
>
> On 4/10/2024 2:12 PM, Dmitry Baryshkov wrote:
> > On Wed, Apr 10, 2024 at 01:18:42PM -0700, Abhinav Kumar wrote:
> >>
> >>
> >> On 4/10/2024 1:16 PM, Dmitry Baryshkov wrote:
> >>>
On Wed, Apr 10, 2024 at 01:18:42PM -0700, Abhinav Kumar wrote:
>
>
> On 4/10/2024 1:16 PM, Dmitry Baryshkov wrote:
> > On Wed, 10 Apr 2024 at 23:00, Abhinav Kumar
> > wrote:
> > >
> > >
> > >
> > > On 12/2/2023 1:40 PM, Dmitry Barysh
On Wed, 10 Apr 2024 at 23:00, Abhinav Kumar wrote:
>
>
>
> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> > Instead of having DPU-specific defines, switch to the definitions from
> > the mdp_common.xml.h file. This is the preparation for merged of DPU and
> > MDP
On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote:
>
>
> On 4/6/24 05:23, Dmitry Baryshkov wrote:
> > On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote:
> > > On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
> > > ab
On Wed, 10 Apr 2024 at 14:53, Aleksandr Mishin wrote:
> On 08.04.2024 12:03, Dmitry Baryshkov wrote:
> > On Mon, 8 Apr 2024 at 11:57, Aleksandr Mishin wrote:
> >>
> >> In dpu_core_irq_callback_handler() callback function pointer is compared
> >> to NULL
On Tue, 9 Apr 2024 at 21:27, Konrad Dybcio wrote:
>
>
>
> On 4/9/24 20:15, Dmitry Baryshkov wrote:
> > On Tue, Apr 09, 2024 at 08:07:56PM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 4/9/24 20:04, Dmitry Baryshkov wrote:
> >>> On Tue, Apr
On Tue, Apr 09, 2024 at 08:07:56PM +0200, Konrad Dybcio wrote:
>
>
> On 4/9/24 20:04, Dmitry Baryshkov wrote:
> > On Tue, Apr 09, 2024 at 10:12:00AM -0700, Rob Clark wrote:
> > > On Tue, Apr 9, 2024 at 8:23 AM Dmitry Baryshkov
> > > wrote:
> > > >
On Tue, Apr 09, 2024 at 10:12:00AM -0700, Rob Clark wrote:
> On Tue, Apr 9, 2024 at 8:23 AM Dmitry Baryshkov
> wrote:
> >
> > On Tue, Apr 09, 2024 at 05:12:46PM +0200, Konrad Dybcio wrote:
> > >
> > >
> > > On 4/6/24 04:56, Dmitry Baryshkov wrote:
>
On Tue, Apr 09, 2024 at 05:13:15PM +0200, Konrad Dybcio wrote:
>
>
> On 4/6/24 05:25, Dmitry Baryshkov wrote:
> > On Fri, Apr 05, 2024 at 10:41:33AM +0200, Konrad Dybcio wrote:
> > > Add speebin data for A740, as found on SM8550 and derivative SoCs.
> > >
&
On Tue, Apr 09, 2024 at 05:12:46PM +0200, Konrad Dybcio wrote:
>
>
> On 4/6/24 04:56, Dmitry Baryshkov wrote:
> > On Fri, Apr 05, 2024 at 10:41:31AM +0200, Konrad Dybcio wrote:
> > > From: Neil Armstrong
> > >
> > > Usually, speedbin 0 is the
On Mon, Apr 08, 2024 at 09:33:01PM -0500, Bjorn Andersson wrote:
> On Tue, Apr 09, 2024 at 01:07:57AM +0300, Dmitry Baryshkov wrote:
> > On Tue, 9 Apr 2024 at 00:23, Abhinav Kumar
> > wrote:
> > > On 4/8/2024 2:12 PM, Dmitry Baryshkov wrote:
> > > > On Mon
https://lore.kernel.org/all/20240409120108.2303d...@canb.auug.org.au/
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 8
drivers/gpu/drm/msm/Makefile| 9 -
drivers/gpu/drm/msm/registers/gen_header.py | 14 +++---
3 files change
On Tue, 9 Apr 2024 at 00:17, Abhinav Kumar wrote:
>
>
>
> On 4/8/2024 2:13 PM, Dmitry Baryshkov wrote:
> > On Tue, 9 Apr 2024 at 00:08, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 4/8/2024 1:41 PM, Bjorn Andersson wrote:
> &g
On Tue, 9 Apr 2024 at 00:23, Abhinav Kumar wrote:
>
>
>
> On 4/8/2024 2:12 PM, Dmitry Baryshkov wrote:
> > On Mon, 8 Apr 2024 at 22:43, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 4/7/2024 11:48 AM, Bjorn Andersson wrote:
> &g
On Tue, 9 Apr 2024 at 00:08, Abhinav Kumar wrote:
>
>
>
> On 4/8/2024 1:41 PM, Bjorn Andersson wrote:
> > On Mon, Apr 08, 2024 at 12:43:34PM -0700, Abhinav Kumar wrote:
> >>
> >>
> >> On 4/7/2024 11:48 AM, Bjorn Andersson wrote:
> >>> On Fri, Apr 05, 2024 at 08:15:47PM -0700, Abhinav Kumar wrote:
On Mon, 8 Apr 2024 at 22:43, Abhinav Kumar wrote:
>
>
>
> On 4/7/2024 11:48 AM, Bjorn Andersson wrote:
> > On Fri, Apr 05, 2024 at 08:15:47PM -0700, Abhinav Kumar wrote:
> >> From: Kuogee Hsieh
> > [..]
> >> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
> >> b/drivers/gpu/drm/msm/dp/dp_displa
8 @@
> * Author: Rob Clark
> */
>
> +#include
> #include
> -#include
> #include
> #include
>
> --
> 2.43.0.rc1.1.gbec44491f096
>
First one didn't reach the PW, let's try again:
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Mon, 8 Apr 2024 at 11:57, Aleksandr Mishin wrote:
>
> In dpu_core_irq_callback_handler() callback function pointer is compared to
> NULL,
> but then callback function is unconditionally called by this pointer.
> Fix this bug by adding conditional return.
>
> Found by Linux Verification Center
On Mon, 8 Apr 2024 at 11:09, Jani Nikula wrote:
>
> On Fri, 05 Apr 2024, Dmitry Baryshkov wrote:
> > On Fri, Apr 05, 2024 at 12:29:07PM +0300, Jani Nikula wrote:
> >> Logging u32 pixel formats using %4.4s format string with a pointer to
> >> the u32 is somewhat ques
On Sat, 30 Mar 2024 at 18:49, Marijn Suijten
wrote:
>
> On 2024-03-30 05:52:29, Dmitry Baryshkov wrote:
> > In case of CMD DSI panels, the vblank IRQ can be used outside of
> > irq_enable/irq_disable pair. This results in the following kind of
>
> Can you clarify when exa
move extra line added
>
> changes in v2:
> - Fix the commit message to explain the scenario
> - Fix the subject a little as well
>
> Fixes: 542b37efc20e ("drm/msm/dp: Implement hpd_notify()")
> Signed-off-by: Kuogee Hsieh
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/dp/dp_display.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
8-dp-connector-type-cleanup-v1-1-9bf84c5a6...@quicinc.com
> ---
> drivers/gpu/drm/msm/dp/dp_display.c | 48
> +
> 1 file changed, 17 insertions(+), 31 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Fri, Apr 05, 2024 at 10:41:28AM +0200, Konrad Dybcio wrote:
> Newer (SM8550+) SoCs don't seem to have a nice speedbin fuse anymore,
> but instead rely on a set of combinations of "feature code" (FC) and
> "product code" (PC) identifiers to match the bins. This series adds
> support for that.
>
On Fri, Apr 05, 2024 at 10:41:33AM +0200, Konrad Dybcio wrote:
> Add speebin data for A740, as found on SM8550 and derivative SoCs.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/driver
On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote:
> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
> abstracted through SMEM, instead of being directly available in a fuse.
>
> Add support for SMEM-based speed binning, which includes getting
> "feature code" and "
On Fri, Apr 05, 2024 at 10:41:31AM +0200, Konrad Dybcio wrote:
> From: Neil Armstrong
>
> Usually, speedbin 0 is the "super SKU", a.k.a the one which can clock
> the highest. Falling back to it when things go wrong is largely
> suboptimal, as more often than not, the top frequencies are not
> sup
On Fri, Apr 05, 2024 at 10:41:29AM +0200, Konrad Dybcio wrote:
> In preparation for parsing the chip "feature code" (FC) and "product
> code" (PC) (essentially the parameters that let us conclusively
> characterize the sillicon we're running on, including various speed
> bins), move the socinfo ver
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