On 10/8/2024 1:00 AM, Neil Armstrong wrote:
Hi,
On 01/10/2024 09:37, neil.armstr...@linaro.org wrote:
Hi,
On 30/09/2024 21:19, Jessica Zhang wrote:
On 9/30/2024 7:17 AM, neil.armstr...@linaro.org wrote:
On 25/09/2024 00:59, Jessica Zhang wrote:
When running igt-test on QRD8650, I
river, through a SCM call.
One place where configuration is expected to be done dynamically is the
QCS6490 rb3gen2.
The downstream driver does this unconditioanlly on any A6xx and newer,
so follow suite and make the call.
Signed-off-by: Bjorn Andersson
Hi Bjorn,
Tested-by: Jessica Zhang # Tr
is is necessary on e.g. QCS6490 Rb3Gen2, in order to avoid "CP | AHB
bus error"-errors from the GPU.
Introduce a function to allow the msm driver to invoke this call.
Signed-off-by: Bjorn Andersson
Hi Bjorn,
Tested-by: Jessica Zhang # Trogdor (sc7180)
Thanks,
Jessica Zhang
On 9/30/2024 7:17 AM, neil.armstr...@linaro.org wrote:
On 25/09/2024 00:59, Jessica Zhang wrote:
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm
On 9/25/2024 1:12 AM, Jani Nikula wrote:
On Tue, 24 Sep 2024, Jessica Zhang wrote:
Add helper to check if the given CRTC state is in clone mode
Signed-off-by: Jessica Zhang
---
include/drm/drm_crtc.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/drm/drm_crtc.h b
On 9/24/2024 4:13 PM, Dmitry Baryshkov wrote:
On Tue, Sep 24, 2024 at 03:59:21PM GMT, Jessica Zhang wrote:
From: Dmitry Baryshkov
All resource allocation is centered around the LMs. Then other blocks
(except DSCs) are allocated basing on the LMs that was selected, and LM
powers up the CRTC
On 9/24/2024 4:16 PM, Dmitry Baryshkov wrote:
On Tue, Sep 24, 2024 at 03:59:22PM GMT, Jessica Zhang wrote:
From: Dmitry Baryshkov
Stop poking into CRTC state from dpu_encoder.c, fill CRTC HW resources
from dpu_crtc_assign_resources().
Signed-off-by: Dmitry Baryshkov
[quic_abhin
On 9/24/2024 4:41 PM, Dmitry Baryshkov wrote:
On Tue, Sep 24, 2024 at 03:59:32PM GMT, Jessica Zhang wrote:
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu
state and add a CWB-specific helper to
reserve the correct CWB muxes and dedicated pingpongs following the
even/odd rule.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 34 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
drivers/gpu/drm/msm/disp
Adjust QoS remapper, OT limit, and CDP parameters to account for
concurrent writeback
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu
kickoff is finished
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 25 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 4 +++-
3 files changed, 24
From: Dmitry Baryshkov
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 +--
drivers/gpu
Add the cwb_enabled flag to msm_display topology and adjust the toplogy
to account for concurrent writeback
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 --
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 --
drivers/gpu/drm/msm/msm_drv.h
num_mixers in CRTC disable
path]
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 32 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 24 ++
2 files changed, 31 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/msm
From: Esha Bharadwaj
Adjust the WB_MUX configuration to account for using dedicated CWB
pingpong blocks.
Signed-off-by: Esha Bharadwaj
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
The CWB mux has a pending flush bit and *_active register.
Add support for configuring them within the dpu_hw_ctl layer.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 13 ++
.../gpu/drm/msm/disp/dpu1
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 83 +-
drivers/gpu/drm/msm/disp/dpu1
Set writeback encoders as possible clones for non-writeback encoders and
vice versa.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 32 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
kicked off to ensure that we don't get timeouts when the
system has a heavy load (ex. when debug logs are enabled)
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 74 ++--
1 file changed, 60 insertions(+), 14 deletions(-)
diff --
The CWB mux has its own registers and set of operations. Add dpu_hw_cwb
abstraction to allow driver to configure the CWB mux.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/Makefile| 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.c | 73
s in dpu_crtc.c
Esha Bharadwaj (3):
drm/msm/dpu: Add CWB entry to catalog for SM8650
drm/msm/dpu: add devcoredumps for cwb registers
drm/msm/dpu: add CWB support to dpu_hw_wb
Jessica Zhang (15):
drm: add clone mode check for CRTC
drm: Add valid clones check
If the clone mode enabled status is changing, a modeset needs to happen
so that the resources can be reassigned
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b
For concurrent writeback, the real time encoder is responsible for
trigger flush and trigger start. Return early for trigger start and
trigger flush for the concurrent writeback encoders.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 ++
1
Check that all encoders attached to a given CRTC are valid
possible_clones of each other.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic_helper.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm
Add support for allocating the concurrent writeback mux as part of the
WB allocation
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 ++
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a
From: Esha Bharadwaj
Implement instance of snapshot function to dump new registers used
for cwb
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Esha Bharadwaj
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 +
1 file changed, 5 insertions(+)
diff --git a
grabbing exising global state]
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 86
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 201 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 19 +++
3 files changed, 183 insertions
Change pingpong index and names to distinguish between general use
pingpong blocks and pingpong blocks dedicated for concurrent writeback
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450
From: Esha Bharadwaj
Add a new block for concurrent writeback mux to the SM8650 HW catalog
Signed-off-by: Esha Bharadwaj
Signed-off-by: Jessica Zhang
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 21 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13
quirements
containing a single field (topology). Remove the useless wrapper.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 71 ++---
drivers/gpu/drm/msm
Add helper to check if the given CRTC state is in clone mode
Signed-off-by: Jessica Zhang
---
include/drm/drm_crtc.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 8b48a1974da3..ecb93e2c4afc 100644
--- a/include/drm/drm_crtc.h
On 9/5/2024 6:30 AM, Dmitry Baryshkov wrote:
On Tue, Sep 03, 2024 at 06:04:13PM GMT, Jessica Zhang wrote:
On 8/30/2024 3:16 PM, Dmitry Baryshkov wrote:
On Fri, 30 Aug 2024 at 22:28, Jessica Zhang wrote:
On 8/30/2024 10:18 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48
On 8/30/2024 3:27 PM, Dmitry Baryshkov wrote:
On Fri, 30 Aug 2024 at 23:28, Jessica Zhang wrote:
On 8/30/2024 10:25 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:35PM GMT, Jessica Zhang wrote:
Reserve dedicated pingpong blocks for CWB
Please explain design ideas. Having just
On 9/4/2024 12:23 PM, Ville Syrjälä wrote:
On Wed, Sep 04, 2024 at 09:41:23PM +0300, Dmitry Baryshkov wrote:
On Wed, 4 Sept 2024 at 01:18, Jessica Zhang wrote:
On 8/30/2024 10:00 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:28PM GMT, Jessica Zhang wrote:
Check that each
On 8/30/2024 3:16 PM, Dmitry Baryshkov wrote:
On Fri, 30 Aug 2024 at 22:28, Jessica Zhang wrote:
On 8/30/2024 10:18 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:32PM GMT, Jessica Zhang wrote:
Add support for allocating the concurrent writeback mux as part of the
WB
On 8/30/2024 10:41 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:31PM GMT, Jessica Zhang wrote:
From: Esha Bharadwaj
Add function ops to allow hw_wb to configure CWB registers and adjust
the WB_MUX configuration to account for using dedicated CWB pingpong
blocks.
Signed-off-by
On 8/30/2024 10:13 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:29PM GMT, Jessica Zhang wrote:
From: Esha Bharadwaj
Add new block for concurrent writeback mux to HW catalog and change
pingpong index names to distinguish between general use pingpong blocks
and pingpong blocks
On 8/30/2024 10:00 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:28PM GMT, Jessica Zhang wrote:
Check that each encoder in the CRTC state's encoder_mask is marked as a
possible clone for all other encoders in the encoder_mask and that only
one CRTC is in clone mode at a
On 8/30/2024 10:47 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:36PM GMT, Jessica Zhang wrote:
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu
On 8/30/2024 10:25 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:35PM GMT, Jessica Zhang wrote:
Reserve dedicated pingpong blocks for CWB
Please explain design ideas. Having just a single phrase is usually not
enough.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm
On 8/30/2024 9:38 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:23PM GMT, Jessica Zhang wrote:
Add clone mode status to the DRM atomic print state
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
On 8/30/2024 10:18 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:32PM GMT, Jessica Zhang wrote:
Add support for allocating the concurrent writeback mux as part of the
WB allocation
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 5
From: Esha Bharadwaj
Add function ops to allow hw_wb to configure CWB registers and adjust
the WB_MUX configuration to account for using dedicated CWB pingpong
blocks.
Signed-off-by: Esha Bharadwaj
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 69
From: Dmitry Baryshkov
Stop poking into CRTC state from dpu_encoder.c, fill CRTC HW resources
from dpu_crtc_assign_resources().
Signed-off-by: Dmitry Baryshkov
[quic_abhin...@quicinc.com: cleaned up formatting]
Signed-off-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm
Adjust QoS remapper, OT limit, and CDP parameters to account for
concurrent writeback
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1
Add support for configuring the CWB pending flush and active bits
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 8 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 13 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 30
grabbing exising global state and
dropped clearing num_mixers in crtc_disable]
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 89 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 201 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
From: Dmitry Baryshkov
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 +--
drivers/gpu
From: Esha Bharadwaj
Add new block for concurrent writeback mux to HW catalog and change
pingpong index names to distinguish between general use pingpong blocks
and pingpong blocks dedicated for concurrent writeback
Signed-off-by: Esha Bharadwaj
Signed-off-by: Jessica Zhang
---
.../drm/msm
For concurrent writeback, the real time encoder is responsible for
trigger flush and trigger start. Return early for trigger start and
trigger flush for the concurrent writeback encoders.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 19 +++
1
Reserve dedicated pingpong blocks for CWB
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 65 +
3 files changed, 79
Add the cwb_enabled flag to msm_display topology and adjust the toplogy
to account for concurrent writeback
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 --
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 11 +--
drivers/gpu/drm/msm/msm_drv.h
resources in dpu_crtc.c
Esha Bharadwaj (3):
drm/msm/dpu: add CWB entry to catalog for SM8650
drm/msm/dpu: add devcoredumps for cwb registers
drm/msm/dpu: add CWB support to dpu_hw_wb
Jessica Zhang (14):
drm: add clone mode check for CRTC
drm: print clone mode status
kicked off to ensure that we don't get timeouts when the
system has a heavy load (ex. when debug logs are enabled)
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 67 ++--
1 file changed, 55 insertions(+), 12 deletions(-)
diff --
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 29 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
quirements
containing a single field (topology). Remove the useless wrapper.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 71 ++---
drivers/gpu/drm/msm
Add support for allocating the concurrent writeback mux as part of the
WB allocation
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 30 +++--
2 files changed, 32 insertions(+), 3
Create a separate API for starting the encoder frame done timer and call
it after the encoder kickoff is finished
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 21 ++---
drivers/gpu/drm/msm
Set writeback encoders as possible clones for non-writeback encoders and
vice versa.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 27 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 7 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
Add helper to check if the given CRTC state is in clone mode
Signed-off-by: Jessica Zhang
---
include/drm/drm_crtc.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 8b48a1974da3..ecb93e2c4afc 100644
--- a/include/drm/drm_crtc.h
From: Esha Bharadwaj
Implement instance of snapshot function to dump new registers used
for cwb
Signed-off-by: Esha Bharadwaj
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1
Add clone mode status to the DRM atomic print state
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 07b4b394e3bf..145d6a758d4d 100644
--- a/drivers/gpu/drm
If the clone mode enabled status is changing, a modeset needs to happen
so that the resources can be reassigned
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers
Check that each encoder in the CRTC state's encoder_mask is marked as a
possible clone for all other encoders in the encoder_mask and that only
one CRTC is in clone mode at a time
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 36 ++
-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 9 -
drivers/gpu/drm/msm/hdmi/hdmi.h| 4 ++--
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 3 +++
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c| 12 ++--
4 files changed, 11
On 5/22/2024 3:51 AM, Dmitry Baryshkov wrote:
The HDMI block needs to be enabled to properly generate HPD events. Make
sure it is not turned off in the disable paths if HPD delivery is enabled.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/hdmi
ch to specifying the HPD property to the
hdmi-connector device.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 14 +++---
drivers/gpu/drm/msm/hdmi/hdmi.h | 2 --
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
On 5/22/2024 3:51 AM, Dmitry Baryshkov wrote:
Expand the HDMI_CFG() macro in HDMI config description. It has no added
value other than hiding some boilerplate declarations.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 16
On 5/22/2024 3:51 AM, Dmitry Baryshkov wrote:
As these clocks are now used in the runtime PM callbacks, they have no
connection to 'HPD'. Rename corresponding fields to follow clocks
purpose, to power up the HDMI controller.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jes
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 62 +-
drivers/gpu/drm/msm/hdmi/hdmi.h| 7 +---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 12 ---
drivers/gpu/drm/msm/hdmi/hdmi_hpd
On 5/22/2024 3:51 AM, Dmitry Baryshkov wrote:
We must be sure that the HDMI controller is powered on, while performing
the DDC transfer. Add corresponding runtime PM calls to
msm_hdmi_i2c_xfer().
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/hdmi
On 5/22/2024 3:50 AM, Dmitry Baryshkov wrote:
The pm_runtime_get_sync() function is a bad choise for runtime power
[nit: s/choise/choice/]
Reviewed-by: Jessica Zhang
management. Switch HDMI driver to pm_runtime_resume_and_get() and add
proper error handling, while we are at it.
Signed
ed-by: Jessica Zhang
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 15 +-
drivers/gpu/drm/msm/hdmi/hdmi.h | 2 +-
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c | 39 +
3 files changed, 19 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/msm
ned-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 2 --
drivers/gpu/drm/msm/hdmi/hdmi.h | 1 -
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c | 9 -
3 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/g
() happening?
IIRC, the msm commit_tail always calls commit_modeset_disables() before
the commit_modeset_enables(). Also, doesn't the pre_enable() and
post_disable() only happen once for bringing up/down the bridge?
Thanks,
Jessica Zhang
iframes will not be updated for the next mode. Fix th
On 5/22/2024 3:50 AM, Dmitry Baryshkov wrote:
In preparation of reworking the HDMI mode setting, switch pre_enable and
post_disable callbacks to their atomic variants.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 15
On 5/22/2024 3:50 AM, Dmitry Baryshkov wrote:
With the extp being the only "power" clock left, remove the surrounding
loops and handle the extp clock directly.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/hdmi/hdmi.c
/e07a5487e521e57f76083c0a6e2f995414ac6d03
Signed-off-by: Dmitry Baryshkov
Hi Dmitry,
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index
: Dmitry Baryshkov
Hi Jun,
LGTM
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 ++-
3 files
On 5/27/2024 7:21 AM, Jun Nie wrote:
data is valid for only half the active window if widebus
is enabled
Signed-off-by: Jun Nie
Hi Jun,
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 9 +
1 file changed, 9 insertions
e only moved to INTF in DPU 7.x and
later.
We should probably add some MDSS version check similar to what command
mode INTF does here [1]
Thanks,
Jessica Zhang
+
hsync_data_start_x = hsync_start_x;
hsync_data_end_x = hsync_start_x + data_width - 1;
--
2.34.1
On 5/27/2024 7:21 AM, Jun Nie wrote:
From: Jonathan Marek
Make it clear why the pkt_per_line value is being "divided by 2".
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jun Nie
Hi Jun,
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
---
Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jun Nie
Hi Jun,
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/d
On 5/27/2024 7:21 AM, Jun Nie wrote:
From: Jonathan Marek
Add width change in DPU timing for DSC compression case to work with
DSI video mode.
Hi Jun,
LGTM
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/drm
by the separate
DRM_DISPLAY_DSC_HELPER Kconfig symbol.
Signed-off-by: Dmitry Baryshkov
Hi Dmitry,
LGTM
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
---
drivers/gpu/drm/amd/amdgpu/Kconfig | 1 +
drivers/gpu/drm/display/Kconfig| 6 ++
drivers/gpu/drm/display/Makefile | 3
_util")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++--
d
coder-fixup-v1-0-585c54cd0...@quicinc.com
---
Jessica Zhang (2):
drm/msm/dpu: Set input_sel bit for INTF
drm/msm/dpu: Drop enable and frame_count parameters from
dpu_hw_setup_misr()
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Signed-off-by: Jessica Zhang
---
drivers/g
On 12/13/2023 1:20 PM, Dmitry Baryshkov wrote:
On Wed, 13 Dec 2023 at 22:51, Jessica Zhang wrote:
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d (&quo
_util")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++--
d
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Signed-off-by: Jessica Zhang
---
drivers/g
in v2:
- Switched patch order
- Changed input_sel parameter from bool to u8
- Link to v1:
https://lore.kernel.org/r/20231130-encoder-fixup-v1-0-585c54cd0...@quicinc.com
---
Jessica Zhang (2):
drm/msm/dpu: Set input_sel bit for INTF
drm/msm/dpu: Drop enable and frame_count parameters
On 12/13/2023 1:00 PM, Abhinav Kumar wrote:
On 12/13/2023 12:51 PM, Jessica Zhang wrote:
Drop the enable and frame_count parameters from dpu_hw_setup_misr() as
they
are always set to the same values.
In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
frame_count is
_util")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++--
d
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Signed-off-by: Jessica Zhang
---
drivers/g
-v1-0-585c54cd0...@quicinc.com
---
Jessica Zhang (2):
drm/msm/dpu: Set input_sel bit for INTF
drm/msm/dpu: Drop enable and frame_count parameters from
dpu_hw_setup_misr()
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
driver
On 12/2/2023 11:54 AM, Dmitry Baryshkov wrote:
On 01/12/2023 23:29, Abhinav Kumar wrote:
On 11/30/2023 11:36 PM, Dmitry Baryshkov wrote:
On Fri, 1 Dec 2023 at 03:31, Jessica Zhang
wrote:
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by
On 11/30/2023 11:39 PM, Dmitry Baryshkov wrote:
On Fri, 1 Dec 2023 at 03:31, Jessica Zhang wrote:
This series drops the frame_count and enable parameters (as they're always
set to the same value). It also sets input_sel=0x1 for INTF.
Signed-off-by: Jessica Zhang
---
Jessica Zha
data |= DSI_VID_CFG0_DATABUS_WIDEN;
Hi Jonathan,
Now that widebus is enabled for video mode, I think you can also drop
the TODO here [1]. Other than that, this LGTM.
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
[1]
https://elixir.bootlin.com/linux/v6.7-rc3/source/drivers/gpu/dr
m/drm_mipi_dsi.h
index c9df0407980c..3e32fa52d94b 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -193,6 +193,7 @@ struct mipi_dsi_device {
unsigned long hs_rate;
unsigned long lp_rate;
struct drm_dsc_config *dsc;
Any reason for not putting
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