On Thu, Jan 23, 2020 at 12:49:03PM +0530, Sharat Masetty wrote:
> This patch adds Adreno 618 entry and its associated properties
> to the gpulist entries.
>
> Signed-off-by: Sharat Masetty
I'm extremely confused - these have been in linux-next for weeks. Why are you
sending them out again?
On Fri, Jan 17, 2020 at 07:32:27PM +0100, Bas Nieuwenhuizen wrote:
> On Fri, Jan 17, 2020 at 7:17 PM Jordan Crouse wrote:
> >
> > On Fri, Jan 17, 2020 at 12:04:17AM +0100, Bas Nieuwenhuizen wrote:
> > > This
> > >
> > > 1) Enables core DRM syncobj suppor
On Fri, Jan 17, 2020 at 12:04:17AM +0100, Bas Nieuwenhuizen wrote:
> This
>
> 1) Enables core DRM syncobj support.
> 2) Adds options to the submission ioctl to wait/signal syncobjs.
>
> Just like the wait fence fd, this does inline waits. Using the
> scheduler would be nice but I believe it is
On Tue, Jan 14, 2020 at 09:30:00AM -0800, Kristian Kristensen wrote:
> On Tue, Jan 14, 2020 at 9:23 AM Jordan Crouse wrote:
> >
> > On Tue, Jan 14, 2020 at 08:52:43AM -0800, Rob Clark wrote:
> > > On Mon, Jan 13, 2020 at 9:51 AM Jordan Crouse
> > > wrote:
>
On Tue, Jan 14, 2020 at 08:41:05AM -0800, Rob Clark wrote:
> On Tue, Jan 14, 2020 at 7:58 AM Jordan Crouse wrote:
> >
> > On Tue, Jan 14, 2020 at 01:40:11AM +0100, Bas Nieuwenhuizen wrote:
> > > On Tue, Jan 14, 2020 at 12:41 AM Jordan Crouse
> > > wrote:
>
On Tue, Jan 14, 2020 at 08:52:43AM -0800, Rob Clark wrote:
> On Mon, Jan 13, 2020 at 9:51 AM Jordan Crouse wrote:
> >
> > On Mon, Jan 13, 2020 at 10:36:05AM -0500, Brian Ho wrote:
> > > +
> > > + vaddr = base_vaddr + args->offset;
> > > +
> &g
s
Reviewed-by: Jordan Crouse
> Fixes: 6a0dea02c2c4 ("drm/msm: support firmware-name for zap fw (v2)")
> Signed-off-by: Douglas Anderson
> ---
>
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --g
On Tue, Jan 14, 2020 at 01:40:11AM +0100, Bas Nieuwenhuizen wrote:
> On Tue, Jan 14, 2020 at 12:41 AM Jordan Crouse wrote:
> >
> > On Mon, Jan 13, 2020 at 09:25:57PM +0100, Bas Nieuwenhuizen wrote:
> > > This
> > >
> > > 1) Enables core DRM syncobj suppor
On Mon, Jan 13, 2020 at 09:25:57PM +0100, Bas Nieuwenhuizen wrote:
> This
>
> 1) Enables core DRM syncobj support.
> 2) Adds options to the submission ioctl to wait/signal syncobjs.
>
> Just like the wait fence fd, this does inline waits. Using the
> scheduler would be nice but I believe it is
On Mon, Jan 13, 2020 at 10:36:04AM -0500, Brian Ho wrote:
> This wait queue is signaled on all IRQs for a given GPU and will be
> used as part of the new MSM_WAIT_IOVA ioctl so userspace can sleep
> until the value at a given iova reaches a certain condition.
>
> Signed-off-by: Brian Ho
> ---
>
On Sun, Jan 12, 2020 at 11:53:58AM -0800, Rob Clark wrote:
> From: Rob Clark
>
> For newer devices we want to require the path to come from the
> firmware-name property in the zap-shader dt node.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drive
y need a single error msg when we can't load from firmware-name
> specified path, and fix comment [Bjorn A.]
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 30 ++---
> 1 file changed, 27 insertion
On Tue, Jan 07, 2020 at 05:38:42PM -0800, Rob Clark wrote:
> From: Rob Clark
>
> Since zap firmware can be device specific, allow for a firmware-name
> property in the zap node to specify which firmware to load, similarly to
> the scheme used for dsp/wifi/etc.
>
> Signed-off-by: Rob Clark
>
On Mon, Dec 16, 2019 at 09:37:50AM -0700, Jordan Crouse wrote:
> Refactor how address space initialization works. Instead of having the
> address space function create the MMU object (and thus require separate but
> equal functions for gpummu and iommu) use a single function and pass
On Tue, Dec 24, 2019 at 08:27:28AM +0530, smase...@codeaurora.org wrote:
> On 2019-12-16 22:07, Jordan Crouse wrote:
> >Attempt to enable split pagetables if the arm-smmu driver supports it.
> >This will move the default address space from the default region to
> >the a
On Fri, Dec 20, 2019 at 03:40:59PM +0530, smase...@codeaurora.org wrote:
> On 2019-12-20 01:28, Jordan Crouse wrote:
> >On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:
> >>The last level system cache can be partitioned to 32 different slices
> >>
On Thu, Dec 19, 2019 at 12:58:15PM -0700, Jordan Crouse wrote:
> On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:
> > +
> > + /*
> > +* CNTL1 is used to specify SCID for (CP, TP, VFD, CCU and UBWC
> > +* FLAG cache) GPU blocks. This
On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:
> The last level system cache can be partitioned to 32 different slices
> of which GPU has two slices preallocated. One slice is used for caching GPU
> buffers and the other slice is used for caching the GPU SMMU pagetables.
> This
On Thu, Dec 19, 2019 at 06:44:45PM +0530, Sharat Masetty wrote:
> Allow different Adreno targets the ability to pass
> specific mmu features to the generic layers. This will
> help conditionally configure certain iommu features for
> certain Adreno targets.
>
> Also Add a few simple support
aggressive cleanups that follow.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c| 23
to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
to start swapping TTBR0 for context-specific pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 52 ++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
/pipermail/iommu/2019-October/039718.html
[2] https://lists.linuxfoundation.org/pipermail/iommu/2019-October/039719.html
[3] https://lists.linuxfoundation.org/pipermail/iommu/2019-October/039720.html
Jordan Crouse (5):
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm-smmu: Add support for split
On Tue, Dec 03, 2019 at 03:06:15PM +, Sharat Masetty wrote:
> Fix the cx debugbus related register configuration, to collect accurate
> bus data during gpu snapshot. This helps with complete snapshot dump
> and also complete proper GPU recovery.
Reviewed-by: Jordan Crouse
This g
On Tue, Dec 03, 2019 at 03:06:11PM +, Sharat Masetty wrote:
> This patch adds support for enabling Graphics Bus Interface(GBIF)
> used in multiple A6xx series chipets. Also makes changes to the
> PDC/RSC sequencing specifically required for A618. This is needed
> for proper interfacing with
On Tue, Dec 03, 2019 at 03:06:12PM +, Sharat Masetty wrote:
> Add the relevant GBIF registers and the debug bus to the a6xx gpu
> state. This comes in pretty handy when debugging GPU bus related
> issues.
>
> Change-Id: I224fda727012a456ccd28ca14caf9fcce236e629
> Signed-off-by: Sharat Masetty
On Sat, Dec 14, 2019 at 05:31:50PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c:2260:3-4: Unneeded semicolon
Reviewed-by: Jordan Crouse
>
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drive
On Sat, Dec 14, 2019 at 05:31:49PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:741:2-3: Unneeded semicolon
>
Reviewed-by: Jordan Crouse
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drivers/gpu/drm/m
On Sat, Dec 14, 2019 at 05:31:47PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/hdmi/hdmi_connector.c:104:3-4: Unneeded semicolon
Reviewed-by: Jordan Crouse
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drivers/gpu/drm/msm/
On Sat, Dec 14, 2019 at 05:31:48PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c:905:2-3: Unneeded semicolon
>
Reviewed-by: Jordan Crouse
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drivers/gpu/drm/
functions to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
aggressive cleanups that follow.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c| 23
but the GMU sneaks out in the middle of the night
and takes the hardware for a joyride.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++--
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++
> 2 files changed, 9 insertions(+
On Sun, Nov 17, 2019 at 06:48:23AM -0500, Brian Masney wrote:
> Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core
> and must use the On Chip MEMory (OCMEM) in order to be functional.
> There's a separate interconnect path that needs to be setup to OCMEM.
> Add support for
On Thu, Nov 14, 2019 at 11:18:56AM +0530, Shubhashree Dhar wrote:
> Current code assumes that all the irqs registers offsets can be
> accessed in all the hw revisions; this is not the case for some
> targets that should not access some of the irq registers.
> This change adds the support to
m that overflow, but is easy to avoid by just converting
> the ktime_t into jiffies directly.
This seems good to me. y2038 changes are the best changes.
Reviewed-by: Jordan Crouse
> Signed-off-by: Arnd Bergmann
> ---
> drivers/gpu/drm/msm/msm_drv.h | 3 +--
> 1 file change
On Tue, Nov 12, 2019 at 01:40:22PM -0300, Fabio Estevam wrote:
> Hi Jordan,
>
> On Fri, Nov 1, 2019 at 11:52 AM Jordan Crouse wrote:
>
> > I'm good with this. This really should only be around for
> > compatibility with downstream device tree files which should mean no
("drm/msm/a6xx: Add a6xx gpu state")
Thanks, I was going to suggest this as well.
> Reviewed-by: Rob Clark
Reviewed-by: Jordan Crouse
> > ---
> > drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 24
> > 1 file changed, 12 insertions(+), 1
On Thu, Oct 31, 2019 at 07:03:59PM -0300, Fabio Estevam wrote:
> Hi Rob,
>
> On Tue, Oct 15, 2019 at 11:19 AM Jeffrey Hugo
> wrote:
> >
> > On Tue, Oct 15, 2019 at 7:40 AM Fabio Estevam wrote:
> > >
> > > Booting the adreno driver on a imx53 board leads to the following
> > > error message:
>
warning: symbol
> 'a5xx_gpu_state_put' was not declared. Should it be static?
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c:1302:6: warning: symbol 'a5xx_show' was
> not declared. Should it be static?
Reviewed-by: Jordan Crouse
> Signed-off-by: Ben Dooks
> ---
> Cc: Rob Clark
> Cc: Sean Paul
>
On Sat, Sep 21, 2019 at 12:04:39PM +0200, khol...@gmail.com wrote:
> From: "Angelo G. Del Regno"
>
> The Adreno 510 GPU is a stripped version of the Adreno 5xx,
> found in low-end SoCs like 8x56 and 8x76, which has 256K of
> GMEM, with no GPMU nor ZAP.
> Also, since the Adreno 5xx part of this
ion-declaration]
>
> Fixes: 482f96324a4e ("drm/msm: Fix task dump in gpu recovery")
Reviewed-by: Jordan Crouse
> Signed-off-by: Arnd Bergmann
> ---
> drivers/gpu/drm/msm/msm_gpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/
On Mon, Sep 16, 2019 at 01:34:55PM -0700, Rob Clark wrote:
> On Mon, Sep 16, 2019 at 1:12 PM Drew Davenport
> wrote:
> >
> > The arguments related to IOMMU port name have been unused since
> > commit 944fc36c31ed ("drm/msm: use upstream iommu") and can be removed.
> >
> > Signed-off-by: Drew
On Fri, Aug 23, 2019 at 05:16:36AM -0700, Brian Masney wrote:
> The files a3xx_gpu.c and a4xx_gpu.c have ifdefs for the OCMEM support
> that was missing upstream. Add two new functions (adreno_gpu_ocmem_init
> and adreno_gpu_ocmem_cleanup) that removes some duplicated code.
Reviewed-b
/iommu/2019-August/038244.html
[5] https://patchwork.freedesktop.org/patch/307601/
Jordan Crouse (7):
iommu/arm-smmu: Support split pagetables
dt-bindings: arm-smmu: Add Adreno GPU variant
iommu/arm-smmu: Add a SMMU variant for the Adreno GPU
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm
-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 28 +
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56
Support the DOMAIN_ATTR_SPLIT_TABLES attribute to let the leaf driver
know if split pagetables are enabled for the domain.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index
Add a new attribute to query the state of split pagetables for the domain.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index fdc355c..b06db6c 100644
--- a/include/linux/iommu.h
+++ b
Add a SMMU model for the Adreno GPU and use it to enable split
pagetable support if the conditions are right.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-impl.c | 15 +++
drivers/iommu/arm-smmu.c | 2 ++
drivers/iommu/arm-smmu.h | 1 +
3 files changed, 18
On Fri, Aug 16, 2019 at 08:43:53PM +0100, Robin Murphy wrote:
> On 16/08/2019 19:12, Rob Clark wrote:
> >On Fri, Aug 16, 2019 at 9:58 AM Robin Murphy wrote:
> >>
> >>Hi Jordan,
> >>
> >>On 15/08/2019 16:33, Jordan Crouse wrote:
> >>>On W
On Wed, Aug 07, 2019 at 04:42:31PM -0700, Stephen Boyd wrote:
> Quoting Jordan Crouse (2019-08-05 13:33:46)
> > The macro to generate a Bus Controller Manager (BCM) TCS command is used
> > by the interconnect driver but might also be interesting to other
> > drivers that
Now that CONFIG_DRM_MSM is no longer default 'y' add it as a module to all
ARCH_QCOM enabled defconfigs to restore the previous expected build
behavior.
Signed-off-by: Jordan Crouse
---
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/configs/qcom_defconfig | 1 +
arch/arm64/configs
Remove the default for CONFIG_DRM_MSM and let the user select the driver
manually as one does.
Additionally select QCOM_COMMAND_DB for ARCH_QCOM targets to make sure
it doesn't get missed when we need it for a6xx targets.
v2: Move from default 'm' to no default
Signed-off-by: Jordan Crouse
Add a new sub-format ARM_ADRENO_GPU_LPAE to set up TTBR0 and TTBR1 for
use by the Adreno GPU. This will allow The GPU driver to map global
buffers in the TTBR1 and leave the TTBR0 configured but unset and
free to be changed dynamically by the GPU.
Signed-off-by: Jordan Crouse
---
drivers/iommu
Add support for an Adreno GPU variant of the arm-smmu device to enable
a special pagetable format that enables TTBR1 and leaves TTBR0 free
to be switched by the GPU hardware.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion
a look and give some advice on the
direction.
[1] https://patchwork.freedesktop.org/series/63403/
Jordan
Jordan Crouse (2):
iommu/io-pgtable-arm: Add support for ARM_ADRENO_GPU_LPAE io-pgtable
format
iommu/arm-smmu: Add support for Adreno GPU pagetable formats
drivers/iommu/arm-smmu.c
.
[1] https://patchwork.freedesktop.org/series/63403/
Jordan
Jordan Crouse (2):
iommu/io-pgtable-arm: Add support for ARM_ADRENO_GPU_LPAE io-pgtable
format
iommu/arm-smmu: Add support for Adreno GPU pagetable formats
drivers/iommu/arm-smmu.c | 8 +-
drivers/iommu/io-pgtable-arm.c
Add a new sub-format ARM_ADRENO_GPU_LPAE to set up TTBR0 and TTBR1 for
use by the Adreno GPU. This will allow The GPU driver to map global
buffers in the TTBR1 and leave the TTBR0 configured but unset and
free to be changed dynamically by the GPU.
Signed-off-by: Jordan Crouse
---
drivers/iommu
On Wed, Aug 07, 2019 at 11:08:53AM -0700, Rob Clark wrote:
> On Wed, Aug 7, 2019 at 10:38 AM Sam Ravnborg wrote:
> >
> > Hi Jordan.
> > On Wed, Aug 07, 2019 at 11:24:27AM -0600, Jordan Crouse wrote:
> > > Most use cases for DRM_MSM will prefer to build both DR
it in.
Additionally select QCOM_COMMAND_DB for ARCH_QCOM targets to make sure
it doesn't get missed when we need it for a6xx tarets.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers
The macro to generate a Bus Controller Manager (BCM) TCS command is used
by the interconnect driver but might also be interesting to other
drivers that need to construct TCS commands for sub processors so move
it out of the sdm845 specific file and into the header.
Signed-off-by: Jordan Crouse
Remove the homebrewed bulk clock get function and replace it with
devm_clk_bulk_get_all().
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
drivers/gpu/drm/msm/msm_drv.c | 40 ---
drivers/gpu/drm/msm/msm_drv.h | 1
Explicitly mark intentional fall throughs in switch statements to keep
-Wimplicit-fallthrough from complaining.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 +
3 files
On Thu, Jul 25, 2019 at 11:52:39AM +0800, Yue Hu wrote:
> From: Yue Hu
>
> Since governor name is defined by DEVFREQ framework internally, use the
> macro definition instead of using the name directly.
Acked-by: Jordan Crouse for the msm part.
> Signed-off-by: Yue Hu
> ---
ker_thread+0x40/0x438
> kthread+0x12c/0x130
> ret_from_fork+0x10/0x18
>---[ end trace afc0dc5ab81a06bf ]---
>
> Not quite sure what triggered that, but we really shouldn't be abusing
> dma_{map,unmap}_sg() for cache maint.
I'm sure we'll see this rear its head again someday. My
it available
for future efforts into this area.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/msm/adreno/a6xx_hfi.c#n219
Signed-off-by: Jordan Crouse
---
drivers/interconnect/qcom/sdm845.c | 17 -
include/soc/qcom/tcs.h | 17
before we need to.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
>
On Sun, Jun 30, 2019 at 06:14:41AM -0700, Rob Clark wrote:
> From: Rob Clark
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_gp
On Wed, Jul 10, 2019 at 05:45:37PM +0100, Robin Murphy wrote:
> Hi Jordan,
>
> On 08/07/2019 20:00, Jordan Crouse wrote:
> >Add a new sub-format ARM_64_LPAE_SPLIT_S1 to create and set up split
> >pagetables (TTBR0 and TTBR1). The initialization function sets up the
> &
pagetable is selected based on the incoming iova but
most of the heavy lifting is common to the other formats.
Signed-off-by: Jordan Crouse
---
drivers/iommu/io-pgtable-arm.c | 261 +
drivers/iommu/io-pgtable.c | 1 +
include/linux/io-pgtable.h
Add a new domain attribute to enable split pagetable support for devices
devices that support it.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index fdc355c..b06db6c 100644
--- a/include
When DOMAIN_ATTR_SPLIT_TABLES is specified for pass ARM_64_LPAE_SPLIT_S1
to io_pgtable_ops to allocate and initialize TTBR0 and TTBR1 pagetables.
v3: Moved all the pagetable specific work into io-pgtable-arm
in a previous patch.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 16
.
This will be used later by the drm/msm driver to enable split pagetables
as part of the effort to implement per-context pagetables [2].
Thanks,
Jordan
[1] https://patchwork.freedesktop.org/series/57441/
[2] https://patchwork.freedesktop.org/patch/307616/?series=57441=3
Jordan Crouse (3):
iommu
Add a new domain attribute to enable split pagetable support for devices
devices that support it.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index fdc355c..b06db6c 100644
--- a/include
-context pagetables [2].
Thanks,
Jordan
[1] https://patchwork.freedesktop.org/series/57441/
[2] https://patchwork.freedesktop.org/patch/307616/?series=57441=3
Jordan Crouse (3):
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/io-pgtable-arm: Add support for AARCH64 split pagetables
iommu/arm-smmu: Add
When DOMAIN_ATTR_SPLIT_TABLES is specified for pass ARM_64_LPAE_SPLIT_S1
to io_pgtable_ops to allocate and initialize TTBR0 and TTBR1 pagetables.
v3: Moved all the pagetable specific work into io-pgtable-arm in a previous
patch.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 16
pagetable is selected based on the incoming iova but
most of the heavy lifting is common to the other formats.
Signed-off-by: Jordan Crouse
---
drivers/iommu/io-pgtable-arm.c | 261 +
drivers/iommu/io-pgtable.c | 1 +
include/linux/io-pgtable.h
> +MODULE_FIRMWARE("qcom/a630_zap.mdt");
> +MODULE_FIRMWARE("qcom/a630_zap.b00");
> +MODULE_FIRMWARE("qcom/a630_zap.b01");
> +MODULE_FIRMWARE("qcom/a630_zap.b02");
Hopefully we are in the very last days of the split PIL so we can leave this
ugliness
On Mon, Jul 01, 2019 at 11:22:35AM +0800, Fuqian Huang wrote:
> Using dev_get_drvdata directly.
msm parts LGTM. If you split the patches feel free to add my
Acked-by: Jordan Crouse
> Signed-off-by: Fuqian Huang
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 6 ++---
iggers an insta-
> reboot, so lets remove the TPL1 registers from the snapshot.
Not to mention that write only registers are incredibly uninteresting for a
snapshot :)
Reviewed-by: Jordan Crouse
> Fixes: 7198e6b03155 drm/msm: add a3xx gpu support
> Signed-off-by: Rob Clark
> ---
&g
On Wed, Jun 19, 2019 at 12:15:26PM -0600, Jordan Crouse wrote:
> On Sun, Jun 16, 2019 at 09:29:30AM -0400, Brian Masney wrote:
> > The files a3xx_gpu.c and a4xx_gpu.c have ifdefs for the OCMEM support
> > that was missing upstream. Add two new functions (adreno
On Sun, Jun 16, 2019 at 09:29:30AM -0400, Brian Masney wrote:
> The files a3xx_gpu.c and a4xx_gpu.c have ifdefs for the OCMEM support
> that was missing upstream. Add two new functions (adreno_gpu_ocmem_init
> and adreno_gpu_ocmem_cleanup) that removes some duplicated code. We also
> need to
On Sun, Jun 16, 2019 at 09:29:26AM -0400, Brian Masney wrote:
> Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and
> must use the On Chip MEMory (OCMEM) in order to be functional. Add the
> optional ocmem property to the Adreno Graphics Management Unit bindings.
>
>
zable gap in coverage since there
seem to be more of these guys in the world than 8996.
Reviewed-by: Jordan Crouse
> ---
>
> v3:
> -Adjusted MERCIU for A540 for best performance.
>
> drivers/gpu/drm/msm/adreno/a5xx.xml.h | 28
> drivers/gpu/drm/m
> It shouldn't be a problem to hook something else up to the IOMMU
> subsystem. Hopefully it's something that people are going to standardize
> on.
>
> > 3) The automatic attach of DMA domain is also causing a different
> >problem for us on the GPU side, preventing us from supporting per-
> >
Before loading the zap shader we should ensure that the reserved memory
region is big enough to hold the loaded file.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno
.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 120 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 19 +
drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 70 +
3 files changed, 192 insertions(+), 17 deletions(-)
diff
Targets that support per-instance pagetable switching will have to keep
track of which pagetable belongs to each instance to be able to recover
for preemption.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
in some of the target files but I think
it pays for itself in improved code flow and flexibility.
v3: change NULl return to ERR_PTR in address space create functions
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 37 --
drivers/gpu/drm/msm/adreno
Add support for creating a auxiliary domain from the IOMMU device to
implement per-instance pagetables. Also add a helper function to
return the pagetable base address (ttbr) and asid to the caller so
that the GPU target code can set up the pagetable switch.
Signed-off-by: Jordan Crouse
Add support to create a GPU target specific address space for
a context. For those targets that support per-instance
pagetables they will return a new address space set up for
the instance if possible otherwise just use the global
device pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu
Add a new domain attribute to enable split pagetable support for devices
devices that support it.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index a815cf6..a2f07cf 100644
--- a/include
Add a helper function to create a GEM address space attached to
an iommu auxiliary domain for a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.h | 4 +++
drivers/gpu/drm/msm/msm_gem_vma.c | 53 +++
2 files changed
.
Jordan Crouse (16):
iommu/arm-smmu: Allow client devices to select direct mapping
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/io-pgtable-arm: Add support for AARCH64 split pagetables
iommu/arm-smmu: Add support for DOMAIN_ATTR_SPLIT_TABLES
iommu: Add DOMAIN_ATTR_PTBASE
iommu/arm-smmu: Add
When we move to 64 bit addressing for a5xx and a6xx targets we will start
seeing pagefaults at larger addresses so format them appropriately in the
log message for easier debugging.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1
generating 32 bit addresses so switch over now to prepare
for using addresses above 4G for targets that support them.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++
2 files changed, 28 insertions
addresses in the pagetable. The driver/hardware is used
to switch the pagetable according to its own specific implementation.
v3: Trivial update to reflect new pgtable ops situation
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 125 +--
1
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path. This clears the way
to change ctx->aspace to a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c| 2 ++
drivers/gpu/d
that the correct
pagetable is selected based on the incoming iova but most of the
heavy lifting is common.
v3: New patch taking most of the TTBR1 specific code out of arm-smmu
Signed-off-by: Jordan Crouse
---
drivers/iommu/io-pgtable-arm.c | 261 +
drivers
Add an attribute to return the base address of the pagetable. This is used
by auxiliary domains from arm-smmu to return the address of the pagetable
to the leaf driver so that it can set the appropriate pagetable through
it's own means.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h
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