On Fri, May 25, 2018 at 04:00:46PM +0530, Sharat Masetty wrote:
> devfreq framework requires the drivers to provide busy time estimations.
> The GPU driver relies on the hardware performance counters for the busy time
> estimations, but different hardware revisions have counters which can be
> sour
On Wed, May 30, 2018 at 08:19:47PM +0530, Rajesh Yadav wrote:
> dpu_io_util.h is moved from standard include path
> to driver folder, correct the include path in code.
>
> Signed-off-by: Rajesh Yadav
If the previous patch doesn't compile without this fix you should squash them.
> ---
> drivers
On Thu, May 31, 2018 at 12:52:03PM +0530, Sharat Masetty wrote:
> This is needed for hardware revisions which do not rely on the generic
> suspend, resume handlers for power management.
>
> Signed-off-by: Sharat Masetty
> ---
> drivers/gpu/drm/msm/msm_gpu.c | 23 +++
> driver
On Thu, May 31, 2018 at 04:01:51PM +0530, Sharat Masetty wrote:
> This patch adds a simple helper function to help write 64 bit payloads
> to the ringbuffer.
>
> Signed-off-by: Sharat Masetty
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12
> drivers/gpu/drm/msm/adreno/a5xx_pow
On Mon, May 28, 2018 at 12:38:41PM +0530, Souptick Joarder wrote:
> On Mon, May 21, 2018 at 10:59 PM, Souptick Joarder
> wrote:
> > Use new return type vm_fault_t for fault handler. For
> > now, this is just documenting that the function returns
> > a VM_FAULT value rather than an errno. Once all
Convert some MASK/SHIFT "registers" into bitmasks, correct the bit positions
for GMU_SPTPRAC_PWR_CLK_STATUS and add a few more definitions.
---
rnndb/adreno/a6xx.xml | 134 ++
rnndb/adreno/a6xx_gmu.xml | 4 +-
2 files changed, 79 insertions(+), 59 deletion
Add a helper function to parse the clock names and set up
the bulk data so we can take advantage of the bulk clock
functions instead of rolling our own. This is added
as a helper function so the upcoming a6xx GMU code can
also take avantage of it.
Signed-off-by: Jordan Crouse
---
drivers/gpu
From: Sharat Masetty
Add initial register headers for A6XX targets.
Signed-off-by: Sharat Masetty
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 1784 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 382 +
2 files changed, 2166 insertions
new files]
*** BLURB HERE ***
Jordan Crouse (2):
drm/msm: Add a helper function to parse clock names
drm/msm: Add A6XX device support
Sharat Masetty (1):
drm/msm: Add generated headers for A6XX
drivers/gpu/drm/msm/Makefile |3 +
drivers/gpu/drm/msm/adreno/a6xx.xml.h
HFI (hardware firmware interface)
queue that the CPU uses to communicate with the GMU.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Makefile |3 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 1174
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 162
On Fri, Jun 08, 2018 at 11:56:04AM +0530, Sharat Masetty wrote:
> This series re-factors the devfreq code a bit in preparation for the upcoming
> A6x related devfreq changes. The code applies cleanly on 4.17 and has been
> verified on DB820C.
>
> V2: Addressed code review comme
of missing firmware.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 0c0eaad68065
, fix issues
identified by smatch]
[v2 - addressed comments from Lucas Stach; added pm_runtime_get_supplier calls
for accesses to the GMU IOMMU; moved to SPDX headers for new files]
Jordan Crouse (4):
drm/msm: Remove pm_runtime operations from msm_iommu
drm/msm: Add a helper function to parse clock
ned-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index b23d33622f37..ccd93ac6a4d8 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.
Add a helper function to parse the clock names and set up
the bulk data so we can take advantage of the bulk clock
functions instead of rolling our own. This is added
as a helper function so the upcoming a6xx GMU code can
also take advantage of it.
Signed-off-by: Jordan Crouse
---
drivers/gpu
HFI (hardware firmware interface)
queue that the CPU uses to communicate with the GMU.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Makefile |3 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 1172
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 162
From: Sharat Masetty
Add initial register headers for A6XX targets.
Signed-off-by: Sharat Masetty
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 1784 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 382 +
2 files changed, 2166 insertions
On Tue, Jun 12, 2018 at 06:17:44PM -0700, Jeykumar Sankaran wrote:
> Subclass drm private state for DPU for handling driver
> specific data. Adds atomic private object and private object
> lock to dpu kms. Provides helper function to retrieve DPU
> private data from current atomic state.
>
> Signe
On Tue, Jun 12, 2018 at 06:17:47PM -0700, Jeykumar Sankaran wrote:
> Switch to state based resource management. This patch
> overhauls the resource manager and HW allocation methods by
> maintaining the global resource pool and allocated hw
> blocks in respective drm component states.
>
> Global r
On Thu, Jun 14, 2018 at 12:30:35PM +0530, Vivek Gautam wrote:
> Hi Jordan,
>
> On Mon, Jun 11, 2018 at 11:56 PM, Jordan Crouse
> wrote:
> > Now that the IOMMU is the master of it's own power we don't need to bring
> > up the GPU to do IOMMU operations. Thi
On Fri, Jun 15, 2018 at 11:05:57PM -0700, Abhinav Kumar wrote:
> Before adding a DSI node to the private list check if the
> node has a valid device connected to it through an endpoint.
>
> This is required in cases where the chipset supports multiple
> DSI hosts but only one of them is being used
f-by: Thomas Zimmermann
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 ++--
> drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
> drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 2 +-
> drivers/gpu/drm/msm/msm_gem_submit.c | 4 ++--
> 4 fil
On Mon, Jun 18, 2018 at 03:11:44PM -0700, abhin...@codeaurora.org wrote:
> Hi Jordan
>
> Thanks for the review.
>
> Comments inline.
>
> Abhinav
> On 2018-06-18 07:23, Jordan Crouse wrote:
> >On Fri, Jun 15, 2018 at 11:05:57PM -0700, Abhinav Kumar wrote:
>
rse ]
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 57 ++
drivers/gpu/drm/msm/msm_drv.h | 4 +++
drivers/gpu/drm/msm/msm_gpu.c | 58 ++-
drivers/gpu/drm/msm/msm_gpu.h | 2 +-
4 files changed, 72 insertions(+),
of missing firmware.
[v2 - fix compile error caused by adreno_load_fw declared static in
adreno_gpu ]
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.c| 2 +-
drivers/gpu/drm/msm/adreno
From: Sharat Masetty
Add initial register headers for A6XX targets.
Signed-off-by: Sharat Masetty
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 1784 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 382 +
2 files changed, 2166 insertions
HFI (hardware firmware interface)
queue that the CPU uses to communicate with the GMU.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Makefile |3 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 1172
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 162
ned-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index b23d33622f37..e80c79b3bb5c 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/g
r new files]
Jordan Crouse (4):
drm/msm: Remove pm_runtime operations from msm_iommu
drm/msm: Add a helper function to parse clock names
drm/msm/adreno: Load the firmware before bringing up the hardware
drm/msm: Add A6XX device support
Sharat Masetty (1):
drm/msm: Add generated headers for
On Thu, Jul 06, 2023 at 09:55:13PM +0300, Dmitry Baryshkov wrote:
>
> On 10/03/2023 00:20, Jordan Crouse wrote:
> > While booting with amd,imageon on a headless target the GPU probe was
> > failing with -ENOSPC in get_pages() from msm_gem.c.
> >
> > Investigation sh
On Tue, Nov 12, 2019 at 01:40:22PM -0300, Fabio Estevam wrote:
> Hi Jordan,
>
> On Fri, Nov 1, 2019 at 11:52 AM Jordan Crouse wrote:
>
> > I'm good with this. This really should only be around for
> > compatibility with downstream device tree files which should me
t overflow, but is easy to avoid by just converting
> the ktime_t into jiffies directly.
This seems good to me. y2038 changes are the best changes.
Reviewed-by: Jordan Crouse
> Signed-off-by: Arnd Bergmann
> ---
> drivers/gpu/drm/msm/msm_drv.h | 3 +--
> 1 file change
On Thu, Nov 14, 2019 at 11:18:56AM +0530, Shubhashree Dhar wrote:
> Current code assumes that all the irqs registers offsets can be
> accessed in all the hw revisions; this is not the case for some
> targets that should not access some of the irq registers.
> This change adds the support to selecti
On Sun, Nov 17, 2019 at 06:48:23AM -0500, Brian Masney wrote:
> Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core
> and must use the On Chip MEMory (OCMEM) in order to be functional.
> There's a separate interconnect path that needs to be setup to OCMEM.
> Add support for this
but the GMU sneaks out in the middle of the night
and takes the hardware for a joyride.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++--
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++
> 2 files changed, 9 insertions(+
/iommu/2019-October/039720.html
Jordan Crouse (8):
dt-bindings: arm-smmu: Add Adreno GPU variant
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context
iommu/arm-smmu: Add split pagetables for Adreno IOMMU implementations
drm/msm: Attach the
aggressive cleanups that follow.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c| 23
functions to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
start swapping TTBR0 for context-specific pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 ++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
On Sat, Dec 14, 2019 at 05:31:48PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c:905:2-3: Unneeded semicolon
>
Reviewed-by: Jordan Crouse
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drivers/gpu/drm/
On Sat, Dec 14, 2019 at 05:31:47PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/hdmi/hdmi_connector.c:104:3-4: Unneeded semicolon
Reviewed-by: Jordan Crouse
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drivers/gpu/drm/msm/
On Sat, Dec 14, 2019 at 05:31:50PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c:2260:3-4: Unneeded semicolon
Reviewed-by: Jordan Crouse
>
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drive
On Sat, Dec 14, 2019 at 05:31:49PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:741:2-3: Unneeded semicolon
>
Reviewed-by: Jordan Crouse
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drivers/gpu/drm/m
On Tue, Dec 03, 2019 at 03:06:12PM +, Sharat Masetty wrote:
> Add the relevant GBIF registers and the debug bus to the a6xx gpu
> state. This comes in pretty handy when debugging GPU bus related
> issues.
>
> Change-Id: I224fda727012a456ccd28ca14caf9fcce236e629
> Signed-off-by: Sharat Masetty
On Tue, Dec 03, 2019 at 03:06:11PM +, Sharat Masetty wrote:
> This patch adds support for enabling Graphics Bus Interface(GBIF)
> used in multiple A6xx series chipets. Also makes changes to the
> PDC/RSC sequencing specifically required for A618. This is needed
> for proper interfacing with RPM
On Tue, Dec 03, 2019 at 03:06:15PM +, Sharat Masetty wrote:
> Fix the cx debugbus related register configuration, to collect accurate
> bus data during gpu snapshot. This helps with complete snapshot dump
> and also complete proper GPU recovery.
Reviewed-by: Jordan Crouse
This guy
/pipermail/iommu/2019-October/039718.html
[2] https://lists.linuxfoundation.org/pipermail/iommu/2019-October/039719.html
[3] https://lists.linuxfoundation.org/pipermail/iommu/2019-October/039720.html
Jordan Crouse (5):
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm-smmu: Add support for split
start swapping TTBR0 for context-specific pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 52 ++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
aggressive cleanups that follow.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c| 23
On Thu, Dec 19, 2019 at 06:44:45PM +0530, Sharat Masetty wrote:
> Allow different Adreno targets the ability to pass
> specific mmu features to the generic layers. This will
> help conditionally configure certain iommu features for
> certain Adreno targets.
>
> Also Add a few simple support functi
On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:
> The last level system cache can be partitioned to 32 different slices
> of which GPU has two slices preallocated. One slice is used for caching GPU
> buffers and the other slice is used for caching the GPU SMMU pagetables.
> This pat
On Thu, Dec 19, 2019 at 12:58:15PM -0700, Jordan Crouse wrote:
> On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:
> > +
> > + /*
> > +* CNTL1 is used to specify SCID for (CP, TP, VFD, CCU and UBWC
> > +* FLAG cache) GPU blocks. This valu
On Fri, Dec 20, 2019 at 03:40:59PM +0530, smase...@codeaurora.org wrote:
> On 2019-12-20 01:28, Jordan Crouse wrote:
> >On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:
> >>The last level system cache can be partitioned to 32 different slices
> >>
On Tue, Dec 24, 2019 at 08:27:28AM +0530, smase...@codeaurora.org wrote:
> On 2019-12-16 22:07, Jordan Crouse wrote:
> >Attempt to enable split pagetables if the arm-smmu driver supports it.
> >This will move the default address space from the default region to
> >the addr
On Mon, Dec 16, 2019 at 09:37:50AM -0700, Jordan Crouse wrote:
> Refactor how address space initialization works. Instead of having the
> address space function create the MMU object (and thus require separate but
> equal functions for gpummu and iommu) use a single function and pass
On Tue, Jan 07, 2020 at 05:38:42PM -0800, Rob Clark wrote:
> From: Rob Clark
>
> Since zap firmware can be device specific, allow for a firmware-name
> property in the zap node to specify which firmware to load, similarly to
> the scheme used for dsp/wifi/etc.
>
> Signed-off-by: Rob Clark
> ---
y need a single error msg when we can't load from firmware-name
> specified path, and fix comment [Bjorn A.]
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 30 ++---
> 1 file changed, 27 insert
On Sun, Jan 12, 2020 at 11:53:58AM -0800, Rob Clark wrote:
> From: Rob Clark
>
> For newer devices we want to require the path to come from the
> firmware-name property in the zap-shader dt node.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drive
On Mon, Jan 13, 2020 at 10:36:05AM -0500, Brian Ho wrote:
> Implements an ioctl to wait until a value at a given iova is greater
> than or equal to a supplied value.
>
> This will initially be used by turnip (open-source Vulkan driver for
> QC in mesa) for occlusion queries where the userspace dri
On Mon, Jan 13, 2020 at 10:36:04AM -0500, Brian Ho wrote:
> This wait queue is signaled on all IRQs for a given GPU and will be
> used as part of the new MSM_WAIT_IOVA ioctl so userspace can sleep
> until the value at a given iova reaches a certain condition.
>
> Signed-off-by: Brian Ho
> ---
>
On Mon, Jan 13, 2020 at 09:25:57PM +0100, Bas Nieuwenhuizen wrote:
> This
>
> 1) Enables core DRM syncobj support.
> 2) Adds options to the submission ioctl to wait/signal syncobjs.
>
> Just like the wait fence fd, this does inline waits. Using the
> scheduler would be nice but I believe it is ou
On Tue, Jan 14, 2020 at 01:40:11AM +0100, Bas Nieuwenhuizen wrote:
> On Tue, Jan 14, 2020 at 12:41 AM Jordan Crouse wrote:
> >
> > On Mon, Jan 13, 2020 at 09:25:57PM +0100, Bas Nieuwenhuizen wrote:
> > > This
> > >
> > > 1) Enables core DRM syncobj suppor
od intentions....
Reviewed-by: Jordan Crouse
> Fixes: 6a0dea02c2c4 ("drm/msm: support firmware-name for zap fw (v2)")
> Signed-off-by: Douglas Anderson
> ---
>
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On Tue, Jan 14, 2020 at 08:52:43AM -0800, Rob Clark wrote:
> On Mon, Jan 13, 2020 at 9:51 AM Jordan Crouse wrote:
> >
> > On Mon, Jan 13, 2020 at 10:36:05AM -0500, Brian Ho wrote:
> > > +
> > > + vaddr = base_vaddr + args->offset;
> > > +
> &g
On Tue, Jan 14, 2020 at 08:41:05AM -0800, Rob Clark wrote:
> On Tue, Jan 14, 2020 at 7:58 AM Jordan Crouse wrote:
> >
> > On Tue, Jan 14, 2020 at 01:40:11AM +0100, Bas Nieuwenhuizen wrote:
> > > On Tue, Jan 14, 2020 at 12:41 AM Jordan Crouse
> > > wrote:
> &
On Tue, Jan 14, 2020 at 09:30:00AM -0800, Kristian Kristensen wrote:
> On Tue, Jan 14, 2020 at 9:23 AM Jordan Crouse wrote:
> >
> > On Tue, Jan 14, 2020 at 08:52:43AM -0800, Rob Clark wrote:
> > > On Mon, Jan 13, 2020 at 9:51 AM Jordan Crouse
> > > wrote:
> &
On Fri, Jan 17, 2020 at 12:04:17AM +0100, Bas Nieuwenhuizen wrote:
> This
>
> 1) Enables core DRM syncobj support.
> 2) Adds options to the submission ioctl to wait/signal syncobjs.
>
> Just like the wait fence fd, this does inline waits. Using the
> scheduler would be nice but I believe it is ou
On Fri, Jan 17, 2020 at 07:32:27PM +0100, Bas Nieuwenhuizen wrote:
> On Fri, Jan 17, 2020 at 7:17 PM Jordan Crouse wrote:
> >
> > On Fri, Jan 17, 2020 at 12:04:17AM +0100, Bas Nieuwenhuizen wrote:
> > > This
> > >
> > > 1) Enables core DRM syncobj suppor
On Thu, Jan 23, 2020 at 12:49:03PM +0530, Sharat Masetty wrote:
> This patch adds Adreno 618 entry and its associated properties
> to the gpulist entries.
>
> Signed-off-by: Sharat Masetty
I'm extremely confused - these have been in linux-next for weeks. Why are you
sending them out again?
Jord
iate place in the shutdown routine and remove the redundant
idle call.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 36 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 43 ---
2 files changed, 31 insertions(+), 48
On Fri, Jan 24, 2020 at 05:50:11PM +0530, Akhil P Oommen wrote:
> Highest bank bit configuration is different for a618 gpu. Update
> it with the correct configuration which is the reset value incidentally.
>
> Signed-off-by: Akhil P Oommen
> Signed-off-by: Sharat Masetty
> ---
> drivers/gpu/drm
On Mon, Jan 27, 2020 at 02:29:53PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 27, 2020 at 1:30 AM Sharat Masetty
> wrote:
> >
> > This patch adds the required dt nodes and properties
> > to enabled A618 GPU.
> >
> > Signed-off-by: Sharat Masetty
> > ---
> > arch/arm64/boot/dts/qcom/sc71
v3: Remove the implementation specific and make split pagetable support
part of the generic configuration
[1] https://lists.linuxfoundation.org/pipermail/iommu/2020-January/041373.html
Jordan Crouse (5):
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm-smmu: Add support for TTBR1
drm/msm: Attach
functions to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Reviewed-by: Rob Clark
Signed-off-by: Jordan Crouse
---
drivers/gpu
start swapping TTBR0 for context-specific pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 52 ++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
aggressive cleanups that follow.
Reviewed-by: Rob Clark
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c
Add support for creating a auxiliary domain from the IOMMU device to
implement per-instance pagetables. Also add a helper function to
return the pagetable base address (ttbr) and asid to the caller so
that the GPU target code can set up the pagetable switch.
Signed-off-by: Jordan Crouse
Targets that support per-instance pagetable switching will have to keep
track of which pagetable belongs to each instance to be able to recover
for preemption.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
Add support for per-instance pagetables for a6xx targets. Add support
to handle split pagetables and create a new instance if the needed
IOMMU support exists and insert the necessary PM4 commands to trigger
a pagetable switch at the beginning of a user command.
Signed-off-by: Jordan Crouse
.html
[2] https://patchwork.freedesktop.org/series/57441/
Jordan Crouse (6):
iommu: Add DOMAIN_ATTR_PTBASE
arm/smmu: Add auxiliary domain support for arm-smmuv2
drm/msm/adreno: ADd support for IOMMU auxiliary domains
drm/msm: Add support to create target specific address spaces
drm/msm/gpu: Add ttbr0 to the me
Add support to create a GPU target specific address space for
a context. For those targets that support per-instance
pagetables they will return a new address space set up for
the instance if possible otherwise just use the global
device pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu
On Fri, Jan 31, 2020 at 08:08:09AM -0800, Doug Anderson wrote:
> Hi,
>
> On Fri, Jan 31, 2020 at 4:16 AM wrote:
> >
> > >> + reg = <0 0x0506a000 0 0x31000>, <0 0x0b29
> > >> 0 0x1>,
> > >> + <0 0x0b49 0 0x1>;
> > >> +
On Mon, Feb 03, 2020 at 04:40:40PM -0800, Rob Clark wrote:
> On Mon, Feb 3, 2020 at 4:21 PM John Stultz wrote:
> >
> > On Wed, Jan 22, 2020 at 11:19 PM Sharat Masetty
> > wrote:
> > >
> > > This patch adds support for enabling Graphics Bus Interface(GBIF)
> > > used in multiple A6xx series chipe
we didn't need to unhalt the GBIF in this path
since the stop function already takes care of that after executing a flush
but before turning off the headswitch. We should be confident that the
GBIF is open for business when we restart the hardware.
Signed-off-by: Jordan Crouse
---
driv
Fixup the GMU bus table values for the sc7180 target.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 85 ---
1 file changed, 60 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
b/drivers/gpu/drm/msm
iate place in the shutdown routine and remove the redundant
idle call.
v2: Remove newly unused variable that was triggering a warning
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 37 +-
drivers/gpu/drm/msm/adreno/a6xx_
On Thu, Feb 06, 2020 at 05:43:52PM +0100, Bas Nieuwenhuizen wrote:
> Hi,
>
> I'd appreciate if you could take a look at this patch. I believe I
> have accommodated the earlier review comments.
Sorry, it was sitting on my todo list. Looks good.
> Thank you,
> Bas
>
> On Fri, Jan 24, 2020 at 12:5
aration introduced in v2
> - Reworked to use ERR_PTR/PTR_ERR
> - Simplified failure gotos.
Reviewed-by: Jordan Crouse
> Signed-off-by: Bas Nieuwenhuizen
> ---
> drivers/gpu/drm/msm/msm_drv.c| 6 +-
> drivers/gpu/drm/msm/msm_gem_submit.c | 232 +++
ix a small memory leak
and free the buffer allocated by nvmem_cell_read().
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/g
mdstream
> buffers.
One nit, but with that:
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_gem.h | 10 ++
> drivers/gpu/drm/msm/msm_gpu.c | 28 +++-
> drivers/gpu/drm/msm/msm_rd.c | 8 +---
>
cmdstream
> buffers.
>
> v2: add missing 'inline'
I should have checked my inbox before responding to v1.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_gem.h | 10 ++
> drivers/gpu/drm/msm/msm_gpu.c | 28 +++
ode. Since we've not yet converted the GMU bindings over to
YAML two patches quickly turn into four but at the end of it we have at least
one bindings file converted to YAML and 99 less lines of code to worry about.
Jordan Crouse (4):
dt-bindings: display: msm: Convert GMU bindings to YAM
The GMU node now requires a specific dma-range property so that the driver
can use the DMA API to do the few memory allocations required by the GMU.
This sets the IOMMU iova allocadtor to match the 'uncached' part of the
GMU virtual address space.
Signed-off-by: Jordan Crouse
---
Doc
The GMU has very few memory allocations and uses a flat memory space so
there is no good reason to go out of our way to bypass the DMA APIs which
were basically designed for this exact secnario.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 107
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings.
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt| 116 --
.../devicetree/bindings/display/msm/gmu.yaml | 130 +
2 files changed
e
Pass false to of_dma_configure so that it fails probe if the DMA region is not
set up.
Jordan Crouse (4):
dt-bindings: display: msm: Convert GMU bindings to YAML
dt-bindings: display: msm: Add required dma-range property
arm64: dts: sdm845: Set the virtual address range for GMU allocations
dr
air should be the size.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
ind
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings.
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt| 116 --
.../devicetree/bindings/display/msm/gmu.yaml | 130 +
2 files changed
from of_dma_configure to fail probe.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 112 +++---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 5 +-
2 files changed, 11 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno
401 - 500 of 1093 matches
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