Marijn Suijten 于2024年9月3日周二 18:12写道：
>
> On 2024-08-29 18:17:32, Jun Nie wrote:
> > Data width for dsc engine is aligned with pipe, not with whole screen
> > width. Because the width may be halved in DSI bonded case.
> >
> > The dsc width is not related to the t
Dmitry Baryshkov 于2024年8月29日周四 19:51写道：
>
> On Thu, 29 Aug 2024 at 13:21, Jun Nie wrote:
> >
> > Blend pipes by left and right. The first 2 pipes are for
> > left half screen and the later 2 pipes are for right in quad
> > pipe case.
> >
> > Signed-off
Dmitry Baryshkov 于2024年8月29日周四 19:38写道：
>
> > @@ -1033,13 +1030,10 @@ static int dpu_plane_atomic_check(struct drm_plane
> > *plane,
> > return -E2BIG;
> > }
> >
> > - /*
> > -* Use multirect for wide plane. We do not support d
Dmitry Baryshkov 于2024年8月29日周四 19:30写道：
>
> On Thu, 29 Aug 2024 at 13:20, Jun Nie wrote:
> >
> > Support 4 pipes and their configs at most. They are for 2 SSPP
> > and their multi-rect mode. Because one SSPP can co-work with
> > 2 mixer at most, 2 pair of mixer
Dmitry Baryshkov 于2024年8月29日周四 19:17写道：
>
> On Thu, 29 Aug 2024 at 13:20, Jun Nie wrote:
> >
> > Add the case to reserve multiple pair mixer for high resolution
>
> I think you already know what is missing here.
Add the case to reserve multiple pair mixer for high resol
Dmitry Baryshkov 于2024年8月29日周四 19:12写道：
>
> On Thu, 29 Aug 2024 at 13:20, Jun Nie wrote:
> >
> > request more mixer for the case that hdisplay exceeding 4096
> > and DSC enabled.
>
> This doesn't seem to match the code. And it misses the _reason_ to do it.
Dmitry Baryshkov 于2024年8月29日周四 19:10写道：
>
> On Thu, 29 Aug 2024 at 13:20, Jun Nie wrote:
> >
> > Do not assume DSC number as 2. Because there are 4 DSC in
> > quad pipe case.
>
> Please expand the commit message. You prefer brevity, but your
> comments lack cla
Dmitry Baryshkov 于2024年8月29日周四 19:07写道：
>
> On Thu, 29 Aug 2024 at 13:19, Jun Nie wrote:
> >
> > Add utility to get mixer number via CRTC handler
> >
> > Signed-off-by: Jun Nie
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 +++
> &g
Dmitry Baryshkov 于2024年8月29日周四 18:57写道：
>
> On Thu, 29 Aug 2024 at 13:19, Jun Nie wrote:
> >
> > Data width for dsc engine is aligned with pipe, not with whole screen
> > width. Because the width may be halved in DSI bonded case.
>
> Can't really parse this.
P
Unify debug info to support dual pipe and quad pipe
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 16 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 35 +--
2 files changed, 21 insertions(+), 30 deletions(-)
diff --git a/drivers
Support quad pipe in general operations with unified method.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 87 +--
1 file changed, 47 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm
There are 2 interface and 4 PP in quad pipe. Map the 2nd
interface to 3rd PP instead of the 2nd PP.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
Blend pipes by left and right. The first 2 pipes are for
left half screen and the later 2 pipes are for right in quad
pipe case.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 13 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 +++---
drivers/gpu
The first 2 fields in multirect_index and stage array are for the first
SSPP and its multi-rect. And the later 2 fields are for the 2nd SSPP
and its multi-rect.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 76 +++-
1 file changed, 55
Support SSPP assignment for quad-pipe case with unified method
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 58 +--
1 file changed, 25 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm
Clip plane into SSPPs per left and right half screen per ROI if topology
is quad pipe. Then split the split rectangle by half if the clip
width still exceed limit.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 97 ++-
1 file changed, 71
Support quad-pipe in SSPP checking with unified method
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 108 ++
1 file changed, 51 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp
Support 4 pipes and their configs at most. They are for 2 SSPP
and their multi-rect mode. Because one SSPP can co-work with
2 mixer at most, 2 pair of mixer are needed for 2 SSPP in quad-
pipe case. So 2 mixer configs are needed in quad-pipe case.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm
operation. While the sspp assignment is in
drm_atomic_helper_check_planes() call tree. So CRTC is more central
than encoder. Siwtching the id achieves above goal.
Co-developed-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1
Support 4 mixers case with increasing array size and checking
the usage case.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 ++-
drivers/gpu
Add the case to reserve multiple pair mixer for high resolution
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 8 +++-
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp
request more mixer for the case that hdisplay exceeding 4096
and DSC enabled.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b
in case of multiple mixer pairs
Signed-off-by: Jun Nie
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index
Do not assume DSC number as 2. Because there are 4 DSC in
quad pipe case.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1
Add utility to get mixer number via CRTC handler
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 5 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm
Add resource allocation type info.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 15b42a6683639
incorrect.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 25 ++---
include/drm/drm_mipi_dsi.h | 2 ++
2 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/d
Data width for dsc engine is aligned with pipe, not with whole screen
width. Because the width may be halved in DSI bonded case.
The dsc width is not related to the timing with back front porch in
later stage, so update dsc timing earlier.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi
that
behave like single panel for display controller.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi.h | 3 ++-
drivers/gpu/drm/msm/dsi/dsi_host.c| 6 +-
drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +-
3 files changed, 8 insertions(+), 3
From: Jonathan Marek
Add support to DSI CTRL v2.8.0 with priority support
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 185d7de0bf376
: Jun Nie
---
Jonathan Marek (3):
drm/msm/dsi: add support to DSI CTRL v2.8.0
drm/msm/dsi: fix DSC width for the bonded DSI case
drm/msm/dsi: support DSC configurations with slice_per_pkt > 1
Jun Nie (18):
drm/msm/dsi: pass the right width to dsc
drm/msm/dpu: polish
From: Jonathan Marek
Make it clear why the pkt_per_line value is being "divided by 2".
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jun Nie
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armst
kov
Signed-off-by: Jun Nie
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8650-HDK
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm
ewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Reviewed-by: Jessica Zhang
Signed-off-by: Jun Nie
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8650-HDK
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 ++-
1 file changed, 2 i
Enable compression bit in cfg2 register for DSC in the DSI case
per hardware version.
Signed-off-by: Jun Nie
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8650-HDK
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm
data is valid for only half the active window if widebus
is enabled
Signed-off-by: Jun Nie
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8650-HDK
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu
From: Jonathan Marek
Add width change in DPU timing for DSC compression case to work with
DSI video mode.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8650-HDK
olish warning usage
- Add tags from reviewers
Changes vs V2:
- Drop the INTF_CFG2_DATA_HCTL_EN change as it is handled in
latest mainline code.
- Drop the bonded DSI patch as I do not have device to test it.
- Address comments from version 2.
Signed-off-by: Jun Nie
---
Changes in v6:
- Link
Dmitry Baryshkov 于2024年5月28日周二 08:48写道：
>
> On Mon, May 27, 2024 at 10:21:48PM +0800, Jun Nie wrote:
> > data is valid for only half the active window if widebus
> > is enabled
> >
> > Signed-off-by: Jun Nie
> > ---
> > drivers/gpu/drm/msm/disp/dp
From: Jonathan Marek
Make it clear why the pkt_per_line value is being "divided by 2".
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/d
kov
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 47f5858334f6..7252d36687e6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/
ewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Reviewed-by: Jessica Zhang
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
ind
Enable compression bit in cfg2 register for DSC in the DSI case
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index
data is valid for only half the active window if widebus
is enabled
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
From: Jonathan Marek
Add width change in DPU timing for DSC compression case to work with
DSI video mode.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8
p the INTF_CFG2_DATA_HCTL_EN change as it is handled in
latest mainline code.
- Drop the bonded DSI patch as I do not have device to test it.
- Address comments from version 2.
Signed-off-by: Jun Nie
---
Changes in v5:
- Link to v4:
https://lore.kernel.org/r/20240524-msm-drm-dsc-dsi-video-upstream-4-v4-0-e61c
From: Jonathan Marek
Make it clear why the pkt_per_line value is being "divided by 2".
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/d
kov
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 47f5858334f6..7252d36687e6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/
ewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Reviewed-by: Jessica Zhang
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
ind
data is valid for only half the active window if widebus
is enabled
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index
From: Jonathan Marek
Add necessary DPU timing and control changes for DSC to work with DSI
video mode.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8
test it.
- Address comments from version 2.
Signed-off-by: Jun Nie
---
Jonathan Marek (4):
drm/msm/dpu: fix video mode DSC for DSI
drm/msm/dsi: set video mode widebus enable bit when widebus is enabled
drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC
drm/msm/dsi: add a comme
Marijn Suijten 于2024年4月9日周二 00:45写道：
>
> Can we drop (fix video mode DSC) from this patch title? It looks like more
> patches are required to get this done, such a mention is more something for
> the
> cover letter.
>
> We could also clarify further to "set Word Count for video-mode DSC".
>
Acce
Dmitry Baryshkov 于2024年4月3日周三 18:51写道：
>
> On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
> >
> > From: Jonathan Marek
> >
> > Support slice_per_pkt in msm driver.
> >
> > Note that the removed "pkt_per_line = slice_per_intf * slice_per_pkt"
>
Dmitry Baryshkov 于2024年4月3日周三 17:41写道：
>
> On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
> >
> > Add variable for slice number of a DSC compression bit stream packet.
> > Its value shall be specified in panel driver, or default value can be set
> > in display controll
Dmitry Baryshkov 于2024年4月3日周三 18:10写道：
>
> On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
> >
> > From: Jonathan Marek
> >
> > The value returned by msm_dsi_wide_bus_enabled() doesn't match what the
> > driver is doing in video mode. Fix that by act
Dmitry Baryshkov 于2024年4月3日周三 17:57写道：
>
> On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
> >
> > From: Jonathan Marek
> >
> > Add necessary DPU timing and control changes for DSC to work with DSI
> > video mode.
> >
> > Signed-of
Dmitry Baryshkov 于2024年4月3日周三 17:49写道：
>
> On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
> >
> > This is follow up update to Jonathan's patch set.
> >
> > Changes vs V2:
> > - Rebase to latest mainline.
> > - Drop the INTF_CFG2_DATA_HCTL_EN change a
From: Jonathan Marek
Support slice_per_pkt in msm driver.
Note that the removed "pkt_per_line = slice_per_intf * slice_per_pkt"
comment is incorrect.
Also trim the code to simplify the dsc reference.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/d
Add variable for slice number of a DSC compression bit stream packet.
Its value shall be specified in panel driver, or default value can be set
in display controller driver if panel driver does not set it.
Signed-off-by: Jun Nie
---
include/drm/display/drm_dsc.h | 4
1 file changed, 4
From: Jonathan Marek
Make it clear why the pkt_per_line value is being "divided by 2".
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/d
From: Jonathan Marek
Video mode DSC won't work if this field is not set correctly. Set it to fix
video mode DSC (for slice_per_pkt==1 cases at least).
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
---
drivers
From: Jonathan Marek
The value returned by msm_dsi_wide_bus_enabled() doesn't match what the
driver is doing in video mode. Fix that by actually enabling widebus for
video mode.
Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI")
Signed-off-by: Jonathan Marek
Signed-
From: Jonathan Marek
Add necessary DPU timing and control changes for DSC to work with DSI
video mode.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8
ff-by: Jun Nie
---
Jonathan Marek (5):
drm/msm/dpu: fix video mode DSC for DSI
drm/msm/dsi: set video mode widebus enable bit when widebus is enabled
drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC (fix video mode DSC)
drm/msm/dsi: add a comment to explain pkt_per_line enc
Dmitry Baryshkov 于2024年3月28日周四 23:05写道：
>
> On Thu, 28 Mar 2024 at 13:12, Jun Nie wrote:
> >
> > Fix DSC timing and control configurations in DPU for DSI video mode.
> > Only compression ratio 3:1 is handled and tested.
> >
> > This patch is modified from patc
- cmd mode + DSC
Signed-off-by: Jun Nie
---
.../gpu/drm/panel/panel-visionox-vtdr6130.c | 58 ++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c
b/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c
index 540099253e1b
Add DSI mode property and compression mode property
Signed-off-by: Jun Nie
---
.../bindings/display/panel/visionox,vtdr6130.yaml | 8
1 file changed, 8 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/panel/visionox,vtdr6130.yaml
b/Documentation
Fix DSC timing and control configurations in DPU for DSI video mode.
Only compression ratio 3:1 is handled and tested.
This patch is modified from patchs of Jonathan Marek.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
.../gpu/drm/msm/disp/dpu1
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