On Thu, Sep 26, 2024 at 2:17 PM Antonino Maniscalco
wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from co
On Thu, Sep 26, 2024 at 2:17 PM Antonino Maniscalco
wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from co
From: Rob Clark
The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
devices (x1-85, possibly others), it seems to pass that barrier while
there are still things in the event completion FIFO waiting to be
written back to memory.
Work around that by adding a fence wait before
On Tue, Sep 24, 2024 at 8:22 AM Akhil P Oommen wrote:
>
> On Tue, Sep 24, 2024 at 07:47:12AM -0700, Rob Clark wrote:
> > On Tue, Sep 24, 2024 at 4:54 AM Antonino Maniscalco
> > wrote:
> > >
> > > On 9/20/24 7:09 PM, Akhil P Oommen wrote:
> > > >
nit, lowercase "a6xx" in subject prefix
(no need to resend just for this, I can fix it up when applying
patches if needed.. but if you do resend pls fix that)
BR
-R
On Tue, Sep 24, 2024 at 4:30 AM Antonino Maniscalco
wrote:
>
> Initialize with 4 rings to enable preemption.
>
> For now only on A
On Wed, Sep 18, 2024 at 9:51 AM Connor Abbott wrote:
>
> On Fri, Sep 13, 2024 at 8:51 PM Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
> > devices (x1-85, possibly others), it seems to p
On Tue, Sep 24, 2024 at 4:54 AM Antonino Maniscalco
wrote:
>
> On 9/20/24 7:09 PM, Akhil P Oommen wrote:
> > On Wed, Sep 18, 2024 at 09:46:33AM +0200, Neil Armstrong wrote:
> >> Hi,
> >>
> >> On 17/09/2024 13:14, Antonino Maniscalco wrote:
> >>> This series implements preemption for A7XX targets,
On Fri, Sep 20, 2024 at 9:54 AM Akhil P Oommen wrote:
>
> On Tue, Sep 17, 2024 at 01:14:19PM +0200, Antonino Maniscalco wrote:
> > Some userspace changes are necessary so add a flag for userspace to
> > advertise support for preemption when creating the submitqueue.
> >
> > When this flag is not s
On Fri, Sep 20, 2024 at 9:15 AM Akhil P Oommen wrote:
>
> On Wed, Sep 18, 2024 at 08:39:30AM -0700, Rob Clark wrote:
> > On Wed, Sep 18, 2024 at 12:46 AM Neil Armstrong
> > wrote:
> > >
> > > Hi,
> > >
> > > On 17/09/2024 13:14, Ant
On Wed, Sep 18, 2024 at 12:46 AM Neil Armstrong
wrote:
>
> Hi,
>
> On 17/09/2024 13:14, Antonino Maniscalco wrote:
> > This series implements preemption for A7XX targets, which allows the GPU to
> > switch to an higher priority ring when work is pushed to it, reducing
> > latency
> > for high pri
On Tue, Sep 17, 2024 at 4:37 PM Konrad Dybcio wrote:
>
> On 17.09.2024 5:30 PM, Rob Clark wrote:
> > On Tue, Sep 17, 2024 at 6:47 AM Konrad Dybcio
> > wrote:
> >>
> >> On 13.09.2024 9:51 PM, Rob Clark wrote:
> >>> From: Rob Clark
> >>
On Tue, Sep 17, 2024 at 6:47 AM Konrad Dybcio wrote:
>
> On 13.09.2024 9:51 PM, Rob Clark wrote:
> > From: Rob Clark
> >
> > The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
> > devices (x1-85, possibly others), it seems to pass that barrier while
From: Rob Clark
The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
devices (x1-85, possibly others), it seems to pass that barrier while
there are still things in the event completion FIFO waiting to be
written back to memory.
Work around that by adding a fence wait before
On Fri, Sep 6, 2024 at 12:59 PM Akhil P Oommen wrote:
>
> On Thu, Sep 05, 2024 at 04:51:18PM +0200, Antonino Maniscalco wrote:
> > This series implements preemption for A7XX targets, which allows the GPU to
> > switch to an higher priority ring when work is pushed to it, reducing
> > latency
> >
On Mon, Sep 9, 2024 at 6:43 AM Connor Abbott wrote:
>
> On Mon, Sep 9, 2024 at 2:15 PM Antonino Maniscalco
> wrote:
> >
> > On 9/6/24 9:54 PM, Akhil P Oommen wrote:
> > > On Thu, Sep 05, 2024 at 04:51:22PM +0200, Antonino Maniscalco wrote:
> > >> This patch implements preemption feature for A6xx
On Fri, Sep 6, 2024 at 5:24 AM Robin Murphy wrote:
>
> On 2024-09-05 6:10 pm, Rob Clark wrote:
> > On Thu, Sep 5, 2024 at 10:00 AM Rob Clark wrote:
> >>
> >> On Thu, Sep 5, 2024 at 9:27 AM Robin Murphy wrote:
> >>>
> >>> On 05/09/2024 4:53
On Thu, Sep 5, 2024 at 10:00 AM Rob Clark wrote:
>
> On Thu, Sep 5, 2024 at 9:27 AM Robin Murphy wrote:
> >
> > On 05/09/2024 4:53 pm, Will Deacon wrote:
> > > Hi Rob,
> > >
> > > On Thu, Sep 05, 2024 at 05:49:56AM -0700, Rob Clark wrote:
> > &g
On Thu, Sep 5, 2024 at 9:27 AM Robin Murphy wrote:
>
> On 05/09/2024 4:53 pm, Will Deacon wrote:
> > Hi Rob,
> >
> > On Thu, Sep 05, 2024 at 05:49:56AM -0700, Rob Clark wrote:
> >> From: Rob Clark
> >>
> >> This reverts commit 85b715a33458348
On Thu, Sep 5, 2024 at 6:24 AM Robin Murphy wrote:
>
> On 05/09/2024 1:49 pm, Rob Clark wrote:
> > From: Rob Clark
> >
> > This reverts commit 85b715a334583488ad7fbd3001fe6fd617b7d4c0.
> >
> > It was causing gpu smmu faults on x1e80100.
> >
> >
From: Rob Clark
This reverts commit 85b715a334583488ad7fbd3001fe6fd617b7d4c0.
It was causing gpu smmu faults on x1e80100.
I _think_ what is causing this is the change in ordering of
__arm_lpae_clear_pte() (dma_sync_single_for_device() on the pgtable
memory) and io_pgtable_tlb_flush_walk
On Wed, Sep 4, 2024 at 6:39 AM Antonino Maniscalco
wrote:
>
> On 8/30/24 8:32 PM, Rob Clark wrote:
> > On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
> > wrote:
> >>
> >> Use the postamble to reset perf counters when switching between rings,
> >>
"qcom,hdmi-tx-8998" compatible
Otto Pflüger (1):
drm/msm/adreno: Add A306A support
Richard Acayan (1):
drm/msm/adreno: add a615 support
Rob Clark (1):
drm/msm: Remove unused pm_state
Sherry Yang (1):
drm/msm: fix %s null argument error
Vladimir Lypak (4):
drm/
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from co
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from co
On Fri, Aug 30, 2024 at 12:09 PM Connor Abbott wrote:
>
> On Fri, Aug 30, 2024 at 8:00 PM Rob Clark wrote:
> >
> > On Fri, Aug 30, 2024 at 11:54 AM Connor Abbott wrote:
> > >
> > > On Fri, Aug 30, 2024 at 7:08 PM Rob Clark wrote:
> > > >
On Fri, Aug 30, 2024 at 11:54 AM Connor Abbott wrote:
>
> On Fri, Aug 30, 2024 at 7:08 PM Rob Clark wrote:
> >
> > On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
> > wrote:
> > >
> > > This patch implements preemption feature for A6xx targets
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
wrote:
>
> Use the postamble to reset perf counters when switching between rings,
> except when sysprof is enabled, analogously to how they are reset
> between submissions when switching pagetables.
>
> Signed-off-by: Antonino Maniscalco
> ---
>
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
wrote:
>
> Initialize with 4 rings to enable preemption.
>
> For now only on A750 as other targets require testing.
>
> Signed-off-by: Antonino Maniscalco
> Tested-by: Neil Armstrong # on SM8650-QRD
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from co
On Wed, Aug 28, 2024 at 6:42 AM Rob Clark wrote:
>
> On Tue, Aug 27, 2024 at 3:56 PM Antonino Maniscalco
> wrote:
> >
> > On 8/27/24 11:07 PM, Rob Clark wrote:
> > > On Tue, Aug 27, 2024 at 1:25 PM Antonino Maniscalco
> > > wrote:
> > >&
On Wed, Aug 28, 2024 at 4:16 AM Konrad Dybcio wrote:
>
> On 27.08.2024 10:12 PM, Rob Clark wrote:
> > resending with updated Konrad email addr
> >
> > On Mon, Aug 26, 2024 at 2:09 PM Rob Clark wrote:
> >>
> >> On Mon, Aug 26, 2024 at 2:07 PM Rob Clark
On Tue, Aug 27, 2024 at 3:56 PM Antonino Maniscalco
wrote:
>
> On 8/27/24 11:07 PM, Rob Clark wrote:
> > On Tue, Aug 27, 2024 at 1:25 PM Antonino Maniscalco
> > wrote:
> >>
> >> On 8/27/24 9:48 PM, Akhil P Oommen wrote:
> >>> On Fri, Aug 2
On Tue, Aug 27, 2024 at 1:25 PM Antonino Maniscalco
wrote:
>
> On 8/27/24 9:48 PM, Akhil P Oommen wrote:
> > On Fri, Aug 23, 2024 at 10:23:48AM +0100, Connor Abbott wrote:
> >> On Fri, Aug 23, 2024 at 10:21 AM Connor Abbott wrote:
> >>>
> >>> On Thu, Aug 22, 2024 at 9:06 PM Akhil P Oommen
> >>>
resending with updated Konrad email addr
On Mon, Aug 26, 2024 at 2:09 PM Rob Clark wrote:
>
> On Mon, Aug 26, 2024 at 2:07 PM Rob Clark wrote:
> >
> > On Fri, Jul 19, 2024 at 3:03 AM Konrad Dybcio
> > wrote:
> > >
> > > This was apparently almost ne
From: Rob Clark
In the case of iova fault triggered devcore dumps, include additional
debug information based on what we think is the current page tables,
including the TTBR0 value (which should match what we have in
adreno_smmu_fault_info unless things have gone horribly wrong), and
the
From: Rob Clark
This series extends io-pgtable-arm with a method to retrieve the page
table entries traversed in the process of address translation, and then
beefs up drm/msm gpu devcore dump to include this (and additional info)
in the devcore dump.
This is a respin of https
On Mon, Aug 26, 2024 at 2:07 PM Rob Clark wrote:
>
> On Fri, Jul 19, 2024 at 3:03 AM Konrad Dybcio
> wrote:
> >
> > This was apparently almost never set on a6xx.. move the existing values
> > and fill out the remaining ones within the catalog.
> >
On Fri, Jul 19, 2024 at 3:03 AM Konrad Dybcio wrote:
>
> This was apparently almost never set on a6xx.. move the existing values
> and fill out the remaining ones within the catalog.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 19 ++-
> dr
From: Rob Clark
In the case of iova fault triggered devcore dumps, include additional
debug information based on what we think is the current page tables,
including the TTBR0 value (which should match what we have in
adreno_smmu_fault_info unless things have gone horribly wrong), and
the
From: Rob Clark
This series extends io-pgtable-arm with a method to retrieve the page
table entries traversed in the process of address translation, and then
beefs up drm/msm gpu devcore dump to include this (and additional info)
in the devcore dump.
This is a respin of https
On Fri, Aug 23, 2024 at 9:09 AM Will Deacon wrote:
>
> On Tue, Aug 20, 2024 at 10:16:44AM -0700, Rob Clark wrote:
> > diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> > index f5d9fd1f45bf..b4bc358740e0 100644
> > --- a/drivers/iommu/io-pgtable
On Fri, Aug 23, 2024 at 9:11 AM Will Deacon wrote:
>
> On Tue, Aug 20, 2024 at 10:16:45AM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > Re-use the generic pgtable walk path.
> >
> > Signed-off-by: Rob Clark
> > --
On Thu, Aug 22, 2024 at 1:34 PM Akhil P Oommen wrote:
>
> On Tue, Aug 20, 2024 at 10:16:47AM -0700, Rob Clark wrote: > From: Rob Clark
>
> >
> > In the case of iova fault triggered devcore dumps, include additional
> > debug information based on what we th
From: Rob Clark
In the case of iova fault triggered devcore dumps, include additional
debug information based on what we think is the current page tables,
including the TTBR0 value (which should match what we have in
adreno_smmu_fault_info unless things have gone horribly wrong), and
the
From: Rob Clark
Add an io-pgtable method to walk the pgtable returning the raw PTEs that
would be traversed for a given iova access.
Signed-off-by: Rob Clark
---
drivers/iommu/io-pgtable-arm.c | 25 +
include/linux/io-pgtable.h | 15 +++
2 files changed
From: Rob Clark
Re-use the generic pgtable walk path.
Signed-off-by: Rob Clark
---
drivers/iommu/io-pgtable-arm.c | 73 +-
1 file changed, 36 insertions(+), 37 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index
From: Rob Clark
We can re-use this basic pgtable walk logic in a few places.
Signed-off-by: Rob Clark
---
drivers/iommu/io-pgtable-arm.c | 59 +-
1 file changed, 36 insertions(+), 23 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io
From: Rob Clark
This series extends io-pgtable-arm with a method to retrieve the page
table entries traversed in the process of address translation, and then
beefs up drm/msm gpu devcore dump to include this (and additional info)
in the devcore dump.
This is a respin of https
limit QCM2290 to RGB formats only
drm/msm/dpu: relax YUV requirements
drm/msm/dpu: take plane rotation into account for wide planes
Rob Clark (1):
drm/msm/adreno: Fix error return if missing firmware-name
drivers/gpu/drm/msm/adreno/adreno_gpu.c| 2 +-
drivers/gpu/drm/msm/dis
On Thu, Aug 15, 2024 at 11:27 AM Antonino Maniscalco
wrote:
>
> This series implements preemption for A7XX targets, which allows the GPU to
> switch to an higher priority ring when work is pushed to it, reducing latency
> for high priority submissions.
>
> This series enables L1 preemption with sk
m the SSPP's fetch configuration is programmed
> to a highest bank bit of 16 as 0x3 translates to 16 and not 14.
>
> Fix the highest bank bit field used for the SSPP to match the mdss
> and gpu settings.
>
> Fixes: 6f410b246209 ("drm/msm/mdss: populate missing data"
On Sun, Aug 11, 2024 at 11:09 PM Akhil P Oommen
wrote:
>
> On Wed, Aug 07, 2024 at 01:34:27PM +0100, Connor Abbott wrote:
> > With a7xx, we need to import a new header for each new generation and
> > switch to a different list of registers, instead of making
> > backwards-compatible changes. Using
From: Rob Clark
This was added in commit ec446d09366c ("drm/msm: call
drm_atomic_helper_suspend() and drm_atomic_helper_resume()"), but unused
since commit ca8199f13498 ("drm/msm/dpu: ensure device suspend happens
during PM sleep") which switched to drm_mode_c
first commit and the giant comment in
> src/freedreno/fdl/fd6_tiled_memcpy.c I've added in [1].
>
> Testing of the Mesa MR both with and without this series is appreciated,
> there are many different SoCs out there with different UBWC
> configurations and I cannot test them all
From: Rob Clark
In the case of iova fault triggered devcore dumps, include additional
debug information based on what we think is the current page tables,
including the TTBR0 value (which should match what we have in
adreno_smmu_fault_info unless things have gone horribly wrong), and
the
From: Rob Clark
Add an io-pgtable method to walk the pgtable returning the raw PTEs that
would be traversed for a given iova access.
Signed-off-by: Rob Clark
Acked-by: Joerg Roedel
---
drivers/iommu/io-pgtable-arm.c | 36 +-
include/linux/io-pgtable.h
From: Rob Clark
This series extends io-pgtable-arm with a method to retrieve the page
table entries traversed in the process of address translation, and then
beefs up drm/msm gpu devcore dump to include this (and additional info)
in the devcore dump.
This is a respin of https
On Tue, Jul 16, 2024 at 2:45 PM Abhinav Kumar wrote:
>
>
>
> On 7/15/2024 12:51 PM, Rob Clark wrote:
> > On Mon, Jul 1, 2024 at 12:43 PM Dmitry Baryshkov
> > wrote:
> >>
> >> On Fri, Jun 28, 2024 at 02:48:47PM GMT, Abhinav Kumar wrote:
> >>>
From: Rob Clark
-ENODEV is used to signify that there is no zap shader for the platform,
and the CPU can directly take the GPU out of secure mode. We want to
use this return code when there is no zap-shader node. But not when
there is, but without a firmware-name property. This case we want
On Thu, Jul 11, 2024 at 3:02 AM Vladimir Lypak wrote:
>
> Fine grain preemption (switching from/to points within submits)
> requires extra handling in command stream of those submits, especially
> when rendering with tiling (using GMEM). However this handling is
> missing at this point in mesa (an
On Mon, Jul 1, 2024 at 12:43 PM Dmitry Baryshkov
wrote:
>
> On Fri, Jun 28, 2024 at 02:48:47PM GMT, Abhinav Kumar wrote:
> > There is no recovery mechanism in place yet to recover from mmu
> > faults for DPU. We can only prevent the faults by making sure there
> > is no misconfiguration.
> >
> > R
/gpu: fix the schema being not applied
Neil Armstrong (2):
drm/msm/adreno: fix a7xx gpu init
drm/msm/adreno: fix a743 and a740 cx mem init
Rob Clark (11):
drm/msm/adreno: Split up giant device table
drm/msm/adreno: Split catalog into separate files
drm/msm/adreno: Move hwcg
On Tue, Jul 2, 2024 at 5:56 AM Connor Abbott wrote:
>
> According to downstream we should be setting RBBM_NC_MODE_CNTL to a
> non-default value on a663 and a680, we don't support a663 and on a680
> we're leaving it at the wrong (suboptimal) value. Just set it on all
> GPUs. Similarly, plumb throug
From: Rob Clark
Fixes a sparse "different address spaces" error.
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202406280050.syeewlte-...@intel.com/
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c | 2 +-
1 file changed, 1 insertion(+),
From: Rob Clark
The __build_asserts() function only exists to have a place to put
build-time asserts.
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202407010401.rfunrbsx-...@intel.com/
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 2
On Fri, Jun 28, 2024 at 2:49 PM Abhinav Kumar wrote:
>
> Introduce a new API msm_iommu_disp_new() for display use-cases.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/msm_iommu.c | 26 ++
> drivers/gpu/drm/msm/msm_mmu.h | 1 +
> 2 files changed, 27 inser
On Fri, Jun 28, 2024 at 6:58 PM Akhil P Oommen wrote:
>
> On Tue, Jun 18, 2024 at 09:42:47AM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > Split into a separate table per generation, in preparation to move each
> > gen's device table to it's ow
On Thu, Jun 27, 2024 at 1:53 PM Abhinav Kumar wrote:
>
> On QCM2290 chipset DPU does not support UBWC.
>
> Add a dpu cap to indicate this and do not expose compressed formats
> in this case.
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 +
>
On Wed, Jun 26, 2024 at 2:38 PM Konrad Dybcio wrote:
>
> On 26.06.2024 8:43 PM, Rob Clark wrote:
> > On Wed, Jun 26, 2024 at 1:24 AM Akhil P Oommen
> > wrote:
> >>
> >> On Mon, Jun 24, 2024 at 03:53:48PM +0200, Konrad Dybcio wrote:
> >>>
&g
On Wed, Jun 26, 2024 at 1:49 PM Akhil P Oommen wrote:
>
> On Mon, Jun 24, 2024 at 07:28:06AM -0700, Rob Clark wrote:
> > On Mon, Jun 24, 2024 at 7:25 AM Rob Clark wrote:
> > >
> > > On Sun, Jun 23, 2024 at 4:08 AM Akhil P Oommen
> > > wrote:
> >
From: Rob Clark
In the case of iova fault triggered devcore dumps, include additional
debug information based on what we think is the current page tables,
including the TTBR0 value (which should match what we have in
adreno_smmu_fault_info unless things have gone horribly wrong), and
the
From: Rob Clark
This series extends io-pgtable-arm with a method to retrieve the page
table entries traversed in the process of address translation, and then
beefs up drm/msm gpu devcore dump to include this (and additional info)
in the devcore dump.
This is a respin of https
On Mon, Jun 24, 2024 at 8:14 AM Will Deacon wrote:
>
> On Thu, May 23, 2024 at 10:52:21AM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > Add an io-pgtable method to walk the pgtable returning the raw PTEs that
> > would be traversed for a given iova access.
&g
On Wed, Jun 26, 2024 at 1:24 AM Akhil P Oommen wrote:
>
> On Mon, Jun 24, 2024 at 03:53:48PM +0200, Konrad Dybcio wrote:
> >
> >
> > On 6/23/24 13:06, Akhil P Oommen wrote:
> > > Add support in drm/msm driver for the Adreno X185 gpu found in
> > > Snapdragon X1 Elite chipset.
> > >
> > > Signed-of
On Tue, Jun 25, 2024 at 1:18 PM Dmitry Baryshkov
wrote:
>
> On Tue, 25 Jun 2024 at 21:54, Konrad Dybcio wrote:
> >
> > Commit c9707bcbd0f3 ("drm/msm/adreno: De-spaghettify the use of memory
>
> ID is not present in next
it ofc wouldn't be, because it was the previous patch in this series ;-)
I'
On Tue, Jun 25, 2024 at 1:23 PM Akhil P Oommen wrote:
>
> On Tue, Jun 25, 2024 at 11:03:42AM -0700, Rob Clark wrote: > On Tue, Jun 25,
> 2024 at 10:59 AM Akhil P Oommen wrote:
> > >
> > > On Fri, Jun 21, 2024 at 02:09:58PM -0700, Rob Clark wrote:
> > > &
On Tue, Jun 25, 2024 at 10:59 AM Akhil P Oommen
wrote:
>
> On Fri, Jun 21, 2024 at 02:09:58PM -0700, Rob Clark wrote:
> > On Sat, Jun 8, 2024 at 8:44 AM Kiarash Hajian
> > wrote:
> > >
> > > The driver's memory regions are currently just ioremap()ed,
On Wed, Jun 5, 2024 at 1:10 PM Konrad Dybcio wrote:
>
> Add speebin data for A740, as found on SM8550 and derivative SoCs.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --g
On Wed, Jun 5, 2024 at 1:10 PM Konrad Dybcio wrote:
>
> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
> abstracted through SMEM, instead of being directly available in a fuse.
>
> Add support for SMEM-based speed binning, which includes getting
> "feature code" and "product c
On Tue, Jun 25, 2024 at 4:27 AM Will Deacon wrote:
>
> On Mon, Jun 24, 2024 at 08:37:26AM -0700, Rob Clark wrote:
> > On Mon, Jun 24, 2024 at 8:14 AM Will Deacon wrote:
> > >
> > > On Thu, May 23, 2024 at 10:52:21AM -0700, Rob Clark wrote:
> > > >
On Mon, Jun 24, 2024 at 11:29 AM Dmitry Baryshkov
wrote:
>
> On Mon, 24 Jun 2024 at 20:59, Rob Clark wrote:
> >
> > On Thu, Jun 20, 2024 at 11:48 PM Luca Weiss
> > wrote:
> > >
> > > On Fri Jun 21, 2024 at 12:47 AM CEST, Konrad Dybcio wrote:
> &
On Thu, Jun 20, 2024 at 11:48 PM Luca Weiss wrote:
>
> On Fri Jun 21, 2024 at 12:47 AM CEST, Konrad Dybcio wrote:
> >
> >
> > On 6/20/24 20:24, Dmitry Baryshkov wrote:
> > > On Thu, 20 Jun 2024 at 20:32, Rob Clark wrote:
> > >>
> > >> On
On Mon, Jun 24, 2024 at 8:14 AM Will Deacon wrote:
>
> On Thu, May 23, 2024 at 10:52:21AM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > Add an io-pgtable method to walk the pgtable returning the raw PTEs that
> > would be traversed for a given iova access.
&g
On Mon, Jun 24, 2024 at 7:25 AM Rob Clark wrote:
>
> On Sun, Jun 23, 2024 at 4:08 AM Akhil P Oommen
> wrote:
> >
> > Add support in drm/msm driver for the Adreno X185 gpu found in
> > Snapdragon X1 Elite chipset.
> >
> > Signed-off-by: Akhil P Oommen
>
On Sun, Jun 23, 2024 at 4:08 AM Akhil P Oommen wrote:
>
> Add support in drm/msm driver for the Adreno X185 gpu found in
> Snapdragon X1 Elite chipset.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++
> drivers/gpu/drm/msm/adreno/a6
On Sat, Jun 8, 2024 at 8:44 AM Kiarash Hajian
wrote:
>
> The driver's memory regions are currently just ioremap()ed, but not
> reserved through a request. That's not a bug, but having the request is
> a little more robust.
>
> Implement the region-request through the corresponding managed
> devres
On Thu, May 30, 2024 at 2:48 AM Marc Gonzalez wrote:
>
> On 16/05/2024 10:43, Marijn Suijten wrote:
>
> > On 2024-05-15 17:09:02, Marc Gonzalez wrote:
> >
> >> When create_address_space() fails (e.g. when smmu node is disabled)
Note that smmu support is going to become a hard dependency with the
On Wed, May 29, 2024 at 3:41 AM Konrad Dybcio wrote:
>
> On 28.05.2024 9:43 PM, Barnabás Czémán wrote:
> > From: Otto Pflüger
> >
> > Add support for Adreno 306A GPU what is found in MSM8917 SoC.
> > This GPU marketing name is Adreno 308.
> >
> > Signed-off-by: Otto Pflüger
> > [use internal nam
On Thu, Jun 20, 2024 at 6:08 AM Dmitry Baryshkov
wrote:
>
> On Thu, 20 Jun 2024 at 00:27, Abhinav Kumar wrote:
> >
> > dpu_encoder_helper_phys_cleanup() calls the ctl ops without checking if
> > the ops are assigned causing discrepancy between its callers where the
> > checks are performed and th
On Tue, Jun 18, 2024 at 12:02 PM Konrad Dybcio wrote:
>
>
>
> On 6/18/24 18:42, Rob Clark wrote:
> > From: Rob Clark
> >
> > Move the CP_PROTECT settings into the hw catalog.
> >
> > Signed-off-by: Rob Clark
> > Reviewed-by: Dmitry Barysh
From: Rob Clark
Move the CP_PROTECT settings into the hw catalog.
Signed-off-by: Rob Clark
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 248 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 257 +-
drivers/gpu/drm/msm
From: Rob Clark
Introduce a6xx_info where we can stash gen specific stuff without
polluting the toplevel adreno_info struct.
Signed-off-by: Rob Clark
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 65 +--
drivers
From: Rob Clark
Move the hwcg tables into the hw catalog.
Signed-off-by: Rob Clark
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 619 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 617
From: Rob Clark
Split each gen's gpu table into it's own file. Only code-motion, no
functional change.
Signed-off-by: Rob Clark
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Konrad Dybcio
---
drivers/gpu/drm/msm/Makefile | 5 +
drivers/gpu/drm/msm/adreno/a2xx_catalo
From: Rob Clark
Split into a separate table per generation, in preparation to move each
gen's device table to it's own file.
Signed-off-by: Rob Clark
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 67 +
From: Rob Clark
Split the single flat gpulist table into per-gen tables that exist in
their own per-gen files, and start moving more info into the device
table. This at least gets all the big tables of register settings out
of the heart of the a6xx_gpu code. Probably more could be moved, to
On Tue, Jun 18, 2024 at 1:30 AM Dmitry Baryshkov
wrote:
>
> On Mon, Jun 17, 2024 at 03:51:14PM GMT, Rob Clark wrote:
> > From: Rob Clark
> >
> > Introduce a6xx_info where we can stash gen specific stuff without
> > polluting the toplevel adreno_info struct.
&g
From: Rob Clark
Introduce a6xx_info where we can stash gen specific stuff without
polluting the toplevel adreno_info struct.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 65 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +--
drivers/gpu/drm
From: Rob Clark
Move the CP_PROTECT settings into the hw catalog.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 247 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 257 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2
From: Rob Clark
Move the hwcg tables into the hw catalog.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 619 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 617 -
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 -
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