Re: [Freedreno] [PATCH 11/21] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor

On Monday 09 July 2018 11:01 PM, Sean Paul wrote: From: Abhinav Kumar Make the pclk_rate u64 to accommodate higher pixel clock rates. Changes in v4: - fixed commit message Signed-off-by: Abhinav Kumar Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++--- 1

[Freedreno] [PATCH 11/21] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor

From: Abhinav Kumar Make the pclk_rate u64 to accommodate higher pixel clock rates. Changes in v4: - fixed commit message Signed-off-by: Abhinav Kumar Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git