Re: [Freedreno] [PATCH v7 1/5] drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe

2022-04-22 Thread Doug Anderson
Hi, On Mon, Mar 21, 2022 at 8:27 PM Vinod Polimera wrote: > > Set mdp clock to max clock rate during probe/bind sequence from the > opp table so that rails are not at undetermined state. Since we do not > know what will be the rate set in boot loader, it would be ideal to > vote at max frequency.

[Freedreno] [PATCH v7 1/5] drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe

2022-03-21 Thread Vinod Polimera
Set mdp clock to max clock rate during probe/bind sequence from the opp table so that rails are not at undetermined state. Since we do not know what will be the rate set in boot loader, it would be ideal to vote at max frequency. There could be a firmware display programmed in bootloader and we wan