Hi All:
In gcc internal, section 16.19.8, there is a rule about
"define_insn_reservation" like:
"`condition` defines what RTL insns are described by this
construction. You should re-
member that you will be in trouble if `condition` for two or more
different `define_insn_
reservation` constructor
On Monday 08 March 2010 16:46:10 Richard Guenther wrote:
> 2010/3/8 Paweł Sikora :
> > hi,
> >
> > during development a cross platform appliacation on x86 workstation
> > i've enabled an alignemnt checking [1] to catch possible erroneous
> > code before it appears on client's sparc/arm cpu with si
On Sat, 2010-03-06 at 11:44 +, Peter Maier wrote:
> The gcc developers seem to have nice tool referred to as "Phil's regression
> hunter". Where can I find documentation on it? I'm interested to know how it
> works and its abilities. Is it maybe even available for download?
>
> - Peter
Long
Jie Zhang wrote:
I'm looking at PR 42258. I have a question on IRA conflict graph and
multiple alternatives.
Below is an RTL insn just before register allocation pass:
(insn 7 6 12 2 pr42258.c:2 (set (reg:SI 136)
(mult:SI (reg:SI 137)
(reg/v:SI 135 [ x ]))) 33 {*thumb_mulsi
2010/3/8 Paweł Sikora :
> hi,
>
> during development a cross platform appliacation on x86 workstation
> i've enabled an alignemnt checking [1] to catch possible erroneous
> code before it appears on client's sparc/arm cpu with sigbus ;)
>
> it works pretty fine and catches alignment violations but
You define STRICT_ALIGNED to be 1 in i386.h or provide an option to
turn that on/off like the rs6000 target does.
Thanks,
Andrew Pinski
Sent from my iPhone
On Mar 8, 2010, at 7:37 AM, Paweł Sikora wrote:
hi,
during development a cross platform appliacation on x86 workstation
i've enabled
I'm looking at PR 42258. I have a question on IRA conflict graph and
multiple alternatives.
Below is an RTL insn just before register allocation pass:
(insn 7 6 12 2 pr42258.c:2 (set (reg:SI 136)
(mult:SI (reg:SI 137)
(reg/v:SI 135 [ x ]))) 33 {*thumb_mulsi3})
IRA generates
hi,
during development a cross platform appliacation on x86 workstation
i've enabled an alignemnt checking [1] to catch possible erroneous
code before it appears on client's sparc/arm cpu with sigbus ;)
it works pretty fine and catches alignment violations but Jakub Jelinek
had told me (on glibc
On Mon, Mar 8, 2010 at 4:27 PM, Frank Isamov wrote:
> On Mon, Mar 8, 2010 at 8:29 AM, Joern Rennecke
> wrote:
>> Quoting Frank Isamov :
>>
>>> Hi,
>>>
>>> I'd like to make a backend which would have 48 bits for 'long' type.
>>> (32 for int and 64 for long long).
>>>
>>> I have tried to define:
>>
On Mon, Mar 8, 2010 at 8:29 AM, Joern Rennecke
wrote:
> Quoting Frank Isamov :
>
>> Hi,
>>
>> I'd like to make a backend which would have 48 bits for 'long' type.
>> (32 for int and 64 for long long).
>>
>> I have tried to define:
>> #define LONG_TYPE_SIZE 48
>
> That's not a partial integer mode
On Mon, Mar 8, 2010 at 9:49 AM, Piotr Wyderski wrote:
> I have the following code:
>
> struct bounding_box {
>
> pack4sf m_Mins;
> pack4sf m_Maxs;
>
> void set(__v4sf v_mins, __v4sf v_maxs) {
>
> m_Mins = v_mins;
> m_Maxs = v_maxs;
> }
> };
>
I have the following code:
struct bounding_box {
pack4sf m_Mins;
pack4sf m_Maxs;
void set(__v4sf v_mins, __v4sf v_maxs) {
m_Mins = v_mins;
m_Maxs = v_maxs;
}
};
struct bin {
bounding_box m_Box[3];
pack4si
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