Machine description question

Hello all, Picochip has communication instructions that allow one array element to pass data to another. There are 3 such instructions PUT/GET/TSTPORT. Currently, all three of these use UNSPEC_VOLATILE side-effect expressions to make sure they don't get reordered. But, i wonder if it is an ove

Re: Build Error

On 05/11/2010 02:00 PM, Diego Novillo wrote: checking libelf.h usability... yes checking libelf.h presence... yes checking for libelf.h... yes checking gelf.h usability... yes checking gelf.h presence... yes checking for gelf.h... yes checking libelf/libelf.h usability... yes checking libelf/li

RE: Machine description question

Our architecture has the similar resource, and we use the first approach by creating an imaginary register and dependency between these instructions, i.e., every such instruction reads and write to the special register to create artificial dependency. You may need to add a (unspec:..) as an indepe

libgcc2

Hi all, is it possible to translate the libgcc2 when i only have 4 registers which are 32 bits long. One of the four Registers is defined as Basepointer and another as Stackpointer. The other two can be used to calculate. Reegards Egge

Re: C++0x Memory model and gcc

Miles Bader wrote: Andrew MacLeod writes: -fmemory-model=single - Enable all data races introductions, as they are today. (relax all 4 internal restrictions.) One could still use this mode with a multi-threaded program as long as explicit synchronization is done, right?

Re: libgcc2

Eggenmüller Bernd writes: > is it possible to translate the libgcc2 when i only have 4 registers > which are 32 bits long. > One of the four Registers is defined as Basepointer and another as > Stackpointer. > The other two can be used to calculate. libgcc2 is intended to be machine independent.

Freescale hc11/12 port extension to s12x / xgate

Announce. I have posted some patches to gcc and binutils to better support Freescale S12X and XGATE cores. See: http://www.msextra.com/tools/s12x-20100504.zip This contains rolled up patches against. gcc-3.3.6 binutils-2.18 newlib-1.16-0 The patches include Stephane Carrez' patches and add binut

Re: Draft SH uClinux FDPIC ABI

On Tue, 25 Mar 2008, Joseph S. Myers wrote: > Following comments on these lists and from Renesas, the revised ABI we > will be implementing is now available. (Further changes may be made for > issues found in the course of implementation.) > > http://www.codesourcery.com/public/docs/sh-fdpic/s

Re: Machine description question

Thanks for your help BingFeng. I gave this a go and ended up with worse code (and worse memory usage) than before. I started with this experiment because of the compilers "All virtual registers are assumed to be used and clobbered by unspec_volatile" rule. The get/put instructions read/write t

Clobbering two registers

Hi all, How can I say in the machine architecture that to generate code for a particular insn I need any two registers for intermediate operations? To get one I think that (clobber (match_operand ...)) will work but what if I want two? Can I add two clobbers on the same define_insn rule? Cheers,

RE: Machine description question

How do you define your imaginary register in target.h? Can you post one example of your instruction pattern? Bingfeng > -Original Message- > From: Hariharan Sandanagobalane [mailto:harihar...@picochip.com] > Sent: 12 May 2010 16:40 > To: Bingfeng Mei > Cc: gcc@gcc.gnu.org > Subject: Re:

Re: Coverage of backend rules

On Tue, May 11, 2010 at 3:26 PM, Ian Lance Taylor wrote: > For define_insn you can use the -da option, and scan the debug files > for the matched insn names.  For define_expand you can reliably use > profiling information to look for calls to gen_NAME. > > This approach won't tell you whether you

Re: Clobbering two registers

"Paulo J. Matos" writes: > How can I say in the machine architecture that to generate code for a > particular insn I need any two registers for intermediate operations? > To get one I think that (clobber (match_operand ...)) will work but > what if I want two? Can I add two clobbers on the same d

Different flags for building plugins and gcc.

On darwin (powerpc only at present, but potentially i686 too) we use "- mdynamic-no-pic" to build the compiler. config/mh-ppc-darwin: # The -mdynamic-no-pic ensures that the compiler executable is built without # position-independent-code -- the usual default on Darwin. This fix speeds # co

PING -- MicroBlaze target support patches

Could someone please review these patches? Add support for Xilinx MicroBlaze processor: http://gcc.gnu.org/ml/gcc-patches/2010-04/msg01903.html http://gcc.gnu.org/ml/gcc-patches/2010-04/msg01905.html http://gcc.gnu.org/ml/gcc-patches/2010-04/msg01908.html http://gcc.gnu.org/ml/gcc-patches/2010-0

Re: Different flags for building plugins and gcc.

IainS writes: > .. this seems a bit strange : -fPIC is not a ld flag... LDFLAGS is flags that are passed to the compiler when linking. It is not flags passed directly to the linker. I don't know why -fPIC is there, but it shouldn't do any harm. The Makefile fragment config/mh-ppc-darwin is s

Re: Different flags for building plugins and gcc.

Hi Ian, On 12 May 2010, at 21:00, Ian Lance Taylor wrote: IainS writes: .. this seems a bit strange : -fPIC is not a ld flag... LDFLAGS is flags that are passed to the compiler when linking. It is not flags passed directly to the linker. I don't know why -fPIC is there, but it shouldn't

mips secondary reload question

Hi: as to page http://gcc.gnu.org/ml/gcc/2010-05/msg00091.html, If the fpu register can not copied to/from memory directly, I have to use intermediate GPR registers. In fact, I return GP_REGS if copying x to a register in class FP_REGS in any mode(including CCmode), this results in infinite recu