Re: [GSoC] How to get started with the isl code generation

2014-05-25 Thread Roman Gareev
Hi Tobias, I tried to incorporate all your comments in the following patch. It also contains traversing of ISL AST and its dump to a file. You can find out more about this at the following link http://romangareev.blogspot.ru/2014/05/gsoc-report-i.html -- Cheers, Roman Gareev patch Description:

RE: Reducing Register Pressure through Live range Shrinking through Loops!!

2014-05-25 Thread Ajit Kumar Agarwal
On Friday, May 23, 2014 1:46 AM Vladimir Makarov wrote: On 05/21/2014 12:25 AM, Ajit Kumar Agarwal wrote: > Hello All: > > Simpson does the Live range shrinking and reduction of register > pressure by using the computation that are not load and store but the > arithmetic computation. The comput

Re: [GSoC] How to get started with the isl code generation

2014-05-25 Thread Tobias Grosser
On 25/05/2014 13:12, Roman Gareev wrote: Hi Tobias, I tried to incorporate all your comments in the following patch. It also contains traversing of ISL AST and its dump to a file. You can find out more about this at the following link http://romangareev.blogspot.ru/2014/05/gsoc-report-i.html

compiler output conflict

2014-05-25 Thread John
I ran across this puzzling difference between gcc and llvm today and think the specification to produce consistent output for this code should be worked out. http://stackoverflow.com/questions/15929795/llvm-and-gcc-different-output-same-code/23856132#23856132 I presented this in the Freenode #gcc

gcc-4.10-20140525 is now available

2014-05-25 Thread gccadmin
Snapshot gcc-4.10-20140525 is now available on ftp://gcc.gnu.org/pub/gcc/snapshots/4.10-20140525/ and on various mirrors, see http://gcc.gnu.org/mirrors.html for details. This snapshot has been generated from the GCC 4.10 SVN branch with the following options: svn://gcc.gnu.org/svn/gcc/trunk

RFA: [VAX] SUBREG of MEM with a mode dependent address

2014-05-25 Thread Matt Thomas
GCC 4.8 for VAX is generating a subreg:HI for mem:SI indexed address. This eventually gets caught by an assert in change_address_1. Since the MEM rtx is SI, legimate_address_p thinks it's fine. I have a change to vax.md which catches these but it's extremely ugly and I have to think there'

Re: negative latencies

2014-05-25 Thread shmeel gutl
On 23-May-14 01:59 PM, Bernd Schmidt wrote: On 05/23/2014 10:07 AM, shmeel gutl wrote: Exposed pipeline is not my problem. Negative latency is my problem. I don't see negative latency for c6x, not in unit reservations and not in adjust cost. Did I miss something? You just need to model it dif

Re: negative latencies

2014-05-25 Thread shmeel gutl
On 23-May-14 05:20 PM, Vladimir Makarov wrote: On 2014-05-23, 3:49 AM, shmeel gutl wrote: On 21-May-14 06:30 PM, Vladimir Makarov wrote: I am just curious what happens when you put insn2, insn1. and insn2 uses a result of insn1 in 6 cycles and insn1 producing the result in 3 cycles, but there

Re: compiler output conflict

2014-05-25 Thread Jakub Jelinek
On Sun, May 25, 2014 at 03:55:38PM -0700, John wrote: > I ran across this puzzling difference between gcc and llvm today and think > the specification to produce consistent output for this code should be worked > out. > http://stackoverflow.com/questions/15929795/llvm-and-gcc-different-output-sam