Re: s390 port

It is unclear how this would even work. For instance, the LA instruction clears the top bit. Also, instructions like LPR, LNR, BXLE, BXH all treat the value in the register as signed, so the top bit is not available. Joe

does aarch64-w64-mingw32 triplet exist??

I am curious whether binutils-gdb/gcc support arm architectures of mingw32. Sent from Mail for Windows

More aggressive threading causing loop-interchange-9.c regression

Hi folks. I have a pending patch for the path solver that pulls in global ranges when available (the stuff in SSA_NAME_RANGE_INFO). In doing so, I have run into a regression I was hoping the loop experts could pontificate on. The regression comes from the simple_reduc_1() function in tree-s

Re: More aggressive threading causing loop-interchange-9.c regression

Hello, On Tue, 7 Sep 2021, Aldy Hernandez via Gcc wrote: > The regression comes from the simple_reduc_1() function in > tree-ssa/loop-interchange-9.c, and it involves the following path: > > === BB 5 > Imports: n_10(D) j_19 > Exports: n_10(D) j_13 j_19 > j_13 : j

Re: s390 port

Hi Joe. Thanks for your comments. > It is unclear how this would even work. > For instance, the LA instruction clears the top bit. In AM64, LA does not clear any bits. > Also, instructions like LPR, LNR, These operate on data registers, not addresses, and will continue to work unchanged. >