Hi,
I've stumbled over a potential issue related to Dataflow analysis,
and maybe you can help me with it. It can be reproduced for AARCH64
but other architectures are affected as well.
I have the next snip before CSE1 pass:
(insn 14 11 15 3 (set (reg:CC 66 cc)
(compare:CC (reg/v:SI 98 [
> However, after this optimization I get the CC reg being dead after
> JUMP_INSN 15, which may lead to wrong code gen. Here it is the dump
> from fwprop1:
>
> (insn 14 11 15 3 (set (reg:CC 66 cc)
> (compare:CC (reg/v:SI 98 [ bytes ])
> (const_int 8 [0x8]))) "bad_cc.c":11:8 406
Hi Eric,
The problem shows in loop-doloop.c when I introduce a loop end pattern
that replaces the first jump instruction (JUMP_INSN 15) with a pattern
that clobbers CC reg. However, the DF doesn't look like it works as
the doloop step cannot find the CC reg alive. Please see
loop-doloop.c:766. Henc
Hi,
I absolutely need your opinion on all these documents attached.
VIEW DOCUMENTS
Have a good working day
Snapshot gcc-10-20221208 is now available on
https://gcc.gnu.org/pub/gcc/snapshots/10-20221208/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 10 git branch
with the following options: git://gcc.gnu.org/git/gcc.git branch
It looks like `-fmodule-file` is better from the discussion. So let's take it.
Thanks for everyone here~
Thanks,
Chuanqi
--
From:Nathan Sidwell
Send Time:2022年12月8日(星期四) 01:00
To:Iain Sandoe ; GCC Development
Cc:Jonathan Wakely ; ch
