[PATCH V2] SSA MATH: Support COND_LEN_FMA for floating-point math optimization

From: Ju-Zhe Zhong Hi, Richard and Richi. Previous patch we support COND_LEN_* binary operations. However, we didn't support COND_LEN_* ternary. Now, this patch support COND_LEN_* ternary. Consider this following case: #define TEST_TYPE(TYPE)

[PATCH 13/14] fortran: Use pre-evaluated class container if available [PR110618]

Add the possibility to provide a pre-evaluated class container argument to gfc_add_finalizer to avoid repeatedly evaluating data reference expressions in the generated code. PR fortran/110618 gcc/fortran/ChangeLog: * trans.h (gfc_add_finalizer_call): Add class container

[Bug target/110643] [13/14 Regression] aarch64: Miscompilation at O1 level (O0 is working)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110643 --- Comment #9 from Mathieu Malaterre --- (In reply to Richard Biener from comment #8) > I wonder if you can try a recent GCC 13 snapshot or the head of the branch > and also confirm with GCC 14 trunk? Could you suggest a docker image I could

[PATCH 09/14] fortran: Inline variable definition

The variable has_finalizer is only used in one place, inline its definition there. gcc/fortran/ChangeLog: * trans.cc (gfc_add_finalizer_call): Inline definition of variable has_finalizer. Merge nested conditions. --- gcc/fortran/trans.cc | 16 +++- 1 file changed, 7

[PATCH 10/14] fortran: Remove redundant argument in get_var_descr

get_var_descr get passed as argument both expr and expr->ts. Remove the type argument which can be retrieved from the other argument. gcc/fortran/ChangeLog: * trans.cc (get_var_descr): Remove argument ts. Use var->ts instead. (gfc_add_finalizer_call): Update caller. ---

[PATCH 08/14] fortran: Push final procedure expr gen close to its one usage.

Final procedure pointer expression is generated in gfc_build_final_call and only used in get_final_proc_ref. Move the generation there. gcc/fortran/ChangeLog: * trans.cc (gfc_add_finalizer_call): Remove local variable final_expr. Pass down expr to get_final_proc_ref and move

[PATCH 12/14] fortran: Factor scalar descriptor generation

The same scalar descriptor generation code is present twice, in the case of derived type entities, and in the case of polymorphic non-coarray entities. Factor it in preparation for a future third case that will also need the same code for scalar descriptor generation. gcc/fortran/ChangeLog:

[PATCH 05/14] fortran: Add missing cleanup blocks

Move cleanup code for the data descriptor after the finalization code as it makes more sense to have it after. Other cleanup blocks should be empty (element size and final pointer are just data references), but add them by the way, just in case. gcc/fortran/ChangeLog: * trans.cc

[PATCH 06/14] fortran: Reuse final procedure pointer expression

Reuse twice the same final procedure pointer expression instead of translating it twice. Final procedure pointer expressions were translated twice, once for the final procedure call, and once for the check for non-nullness (if applicable). gcc/fortran/ChangeLog: * trans.cc

[PATCH 00/14] fortran: Use precalculated class container for deallocation [PR110618]

Hello, the following patches are abot PR110618, a PR similar to PR92178 from which it is cloned. Both are about a problem of dedendencies between arguments, when one of them is associated to an allocatable intent(out) dummy, and thus deallocated in the process of argument association. PR110618

[PATCH 11/14] fortran: Outline virtual table pointer evaluation

gcc/fortran/ChangeLog: * trans.cc (get_vptr): New function. (gfc_add_finalizer_call): Move virtual table pointer evaluation to get_vptr. --- gcc/fortran/trans.cc | 33 ++--- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git

[PATCH 04/14] fortran: Inline gfc_build_final_call

Function gfc_build_final_call has been simplified, inline it. gcc/fortran/ChangeLog: * trans.cc (gfc_build_final_call): Inline... (gfc_add_finalizer_call): ... to its one caller. --- gcc/fortran/trans.cc | 66 +--- 1 file changed, 25

[PATCH 02/14] fortran: Outline element size evaluation

gcc/fortran/ChangeLog: * trans.cc (get_elem_size): New function. (gfc_build_final_call): Outline the element size evaluation to get_elem_size. --- gcc/fortran/trans.cc | 44 ++-- 1 file changed, 30 insertions(+), 14 deletions(-)

[PATCH 03/14] fortran: Outline data reference descriptor evaluation

gcc/fortran/ChangeLog: * trans.cc (get_var_descr): New function. (gfc_build_final_call): Outline the data reference descriptor evaluation code to get_var_descr. --- gcc/fortran/trans.cc | 149 --- 1 file changed, 83 insertions(+),

[PATCH 07/14] fortran: Push element size expression generation close to its usage

gfc_add_finalizer_call creates one expression which is only used by the get_final_proc_ref function. Move the expression generation there. gcc/fortran/ChangeLog: * trans.cc (gfc_add_finalizer_call): Remove local variable elem_size. Pass expression to get_elem_size and move the

[PATCH 01/14] fortran: Outline final procedure pointer evaluation

gcc/fortran/ChangeLog: * trans.cc (get_final_proc_ref): New function. (gfc_build_final_call): Outline the pointer evaluation code to get_final_proc_ref. --- gcc/fortran/trans.cc | 27 +-- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git

[Bug tree-optimization/110640] [13/14 Regression] Wrong code at -O2/3 on x86_64-linux-gnu since GCC-13

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110640 --- Comment #3 from Richard Biener --- We end up with [local count: 78745003]: [local count: 78745003]: *c.5_6 = _7; f.7_32 = f; if (f.7_32 != 0) goto ; [89.00%] else goto ; [11.00%] [local count: 70083053]: f = 0;

Re: analyzer: New state machine should be C++ only

(apologies for top-posting; I'm on vacation and don't have my usual email setup) Sounds interesting, but I'm having difficulty imagining exactly what you have in mind. Can you post one or more concrete examples of buggy code that would be caught by such a warning? Why wouldn't it be caught by

RE: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM

Sure thing, get you point now, will have a try and send v4 if everything goes well. Pan -Original Message- From: Kito Cheng Sent: Thursday, July 13, 2023 3:35 PM To: Li, Pan2 Cc: Jeff Law ; gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; rdapp@gmail.com; Wang, Yanzhang Subject:

Re: [PATCH] RISC-V: Throw compilation error for unknown sub-extension or supervisor extension

Thanks for review. I uploaded version V2, which addresses Kito's comments, along with two changes. The first is to reduce repeated errors, which are currently reported at least twice. The second is to report as many mistakes as possible. V2

[PATCH V2] RISC-V: Throw compilation error for unknown sub-extension or supervisor extension

Hi, This tiny patch add a check for extension starts with 'z' or 's' in `-march` option. Currently this unknown extension will be passed to the assembler, which then reports an error. With this patch, the compiler will throw a compilation error if the extension starts with 'z' or 's' is not a

Re: [PATCH 2/4] [RISC-V] support cm.popretz in zcmp

I was thinking does it possible to using peephole2 to optimize this case, but I realized their is several barrier, like stack tie and note...so it seems hard to just leverage peephole2. And the patch is LGTM, only a few minor coding format issues, but you don't need to send new patch, I can fix

Re: [PATCH] tree-optimization/94864 - vector insert of vector extract simplification

On Thu, Jul 13, 2023 at 2:32 PM Richard Biener wrote: > > On Thu, 13 Jul 2023, Hongtao Liu wrote: > > > On Thu, Jul 13, 2023 at 10:47?AM Hongtao Liu wrote: > > > > > > On Wed, Jul 12, 2023 at 9:37?PM Richard Biener via Gcc-patches > > > wrote: > > > > > > > > The PRs ask for optimizing of > > >

[Bug bootstrap/110646] [14 Regression] gensupport.cc:643:18: error: 'stoi' is not a member of 'std'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110646 Richard Biener changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug tree-optimization/110645] False positive -Warray-bounds warning

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110645 Richard Biener changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

Re: [PATCH 4/4] [RISC-V] support cm.mva01s cm.mvsa01 in zcmp

LGTM, thanks, just like other zc* patches, I would like to defer this until the binutils part landed :) On Wed, Jun 7, 2023 at 1:54 PM Fei Gao wrote: > > From: Die Li > > Signed-off-by: Die Li > Co-Authored-By: Fei Gao > > gcc/ChangeLog: > > * config/riscv/peephole.md: New pattern. >

[Bug target/110643] [13/14 Regression] aarch64: Miscompilation at O1 level (O0 is working)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110643 Richard Biener changed: What|Removed |Added Known to fail||13.1.0 Summary|aarch64:

Re: Re: [PATCH] Add VXRM enum

Oh, sorry for that, thank you very much! XD -Original Messages- From: "Kito Cheng" Sent Time: 2023-07-13 15:24:45 (Thursday) To: "Robin Dapp" Cc: chenyix...@iscas.ac.cn, gcc-patches@gcc.gnu.org, and...@sifive.com, shiyul...@iscas.ac.cn, oriachi...@gmail.com, shi...@iscas.ac.cn,

Re: [PATCH] SSA MATH: Support COND_LEN_FMA for floating-point math optimization

On Thu, 13 Jul 2023, juzhe.zh...@rivai.ai wrote: > From: Ju-Zhe Zhong > > Hi, Richard and Richi. > > Previous patch we support COND_LEN_* binary operations. However, we didn't > support COND_LEN_* ternary. > > Now, this patch support COND_LEN_* ternary. Consider this following case: > >

Re: Re: [PATCH V7] RISC-V: RISC-V: Support gather_load/scatter RVV auto-vectorization

On Thu, Jul 13, 2023 at 1:30 AM 钟居哲 wrote: > > I notice vectorizable_call in Loop Vectorizer. > It's vectorizing CALL function for example like fmax/fmin. > From my understanding, we dont have RVV instruction for fmax/fmin? There's things like .POPCOUNT which we can vectorize, but sure, it

Re: [PATCH] Fix part of PR 110293: `A NEEQ (A NEEQ CST)` part

On Wed, Jul 12, 2023 at 6:09 PM Andrew Pinski via Gcc-patches wrote: > > This fixes part of PR 110293, for the outer comparison case > being `!=` or `==`. In turn PR 110539 is able to be optimized > again as the if statement for `(a&1) == ((a & 1) != 0)` gets optimized > to `false` early enough

Re: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM

oh, I know why you failed on that, you need to put it within the function, not global static, function static variable will construct when first invoked rather than construct at program start. Could you try to apply my diff in the last mail and try again? On Thu, Jul 13, 2023 at 3:29 PM Li, Pan2

Re: [PATCH ver4] rs6000, Add return value to __builtin_set_fpscr_rn

Hi Carl, on 2023/7/12 02:06, Carl Love wrote: > GCC maintainers: > > Ver 4, Removed extra space in subject line. Added comment to commit > log comments about new __SET_FPSCR_RN_RETURNS_FPSCR__ define. Changed > Added to Add and Renamed to Rename in ChangeLog. Updated define_expand >

RE: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM

Thanks Kito for review. Sorry didn't involve the code result in self test error in PATCH v3, but it can be reproduced with below diff based on PATCH v3. Let me know if I didn't get the point of your comments. diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index

Re: [PATCH] Add VXRM enum

Those enum values have been defined via `#pragma riscv intrinsic "vector"` :) https://github.com/gcc-mirror/gcc/commit/01d62e9b6c3e9fd3132f1616843103ccf81778ed On Thu, Jul 13, 2023 at 2:55 PM Robin Dapp via Gcc-patches wrote: > > > +enum __RISCV_VXRM { > > + __RISCV_VXRM_RNU = 0, > > +

[Bug target/104124] Poor optimization for vector splat DW with small consts

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104124 HaoChen Gui changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

Re: [PATCH] Add VXRM enum

> +enum __RISCV_VXRM { > + __RISCV_VXRM_RNU = 0, > + __RISCV_VXRM_RNE = 1, > + __RISCV_VXRM_RDN = 2, > + __RISCV_VXRM_ROD = 3, > +}; > + > __extension__ extern __inline unsigned long > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > vread_csr(enum RVV_CSR csr) We have

[Bug target/110643] aarch64: Miscompilation at O1 level (O0 is working)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110643 --- Comment #7 from Mathieu Malaterre --- (In reply to Andrew Pinski from comment #3) > Does -ffp-contract=on help? Nope, I do not see any difference in symptoms: ``` 73: [ RUN ] HwyMathTestGroup/HwyMathTest.TestAllAtan2/NEON_WITHOUT_AES

Re: [PATCH] tree-optimization/94864 - vector insert of vector extract simplification

On Wed, 12 Jul 2023, Richard Sandiford wrote: > Richard Biener writes: > > The PRs ask for optimizing of > > > > _1 = BIT_FIELD_REF ; > > result_4 = BIT_INSERT_EXPR ; > > > > to a vector permutation. The following implements this as > > match.pd pattern, improving code generation on x86_64.

[Bug target/110643] aarch64: Miscompilation at O1 level (O0 is working)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110643 --- Comment #5 from Mathieu Malaterre --- > We are going to need a self contained testcase to figure this out ... You are not going to like it. Anyway here it goes: [using Debian sid/arm64] $ git clone https://github.com/google/highway.git $

[Bug target/110643] aarch64: Miscompilation at O1 level (O0 is working)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110643 --- Comment #6 from Mathieu Malaterre --- > $ export CXX=-O1 > $ export CXXFLAGS=g++-13 should read: $ export CXX=g++-13 $ export CXXFLAGS=-O1

Re: [PATCH] tree-optimization/94864 - vector insert of vector extract simplification

On Thu, 13 Jul 2023, Hongtao Liu wrote: > On Thu, Jul 13, 2023 at 10:47?AM Hongtao Liu wrote: > > > > On Wed, Jul 12, 2023 at 9:37?PM Richard Biener via Gcc-patches > > wrote: > > > > > > The PRs ask for optimizing of > > > > > > _1 = BIT_FIELD_REF ; > > > result_4 = BIT_INSERT_EXPR ; > > >

[PATCH] Add VXRM enum

From: XYenChi Noticed that the rvv-intrinsic-doc updated the __RISCV_VXRM. gcc/ChangeLog:Add __RISCV_VXRM enum to riscv_vector.h 2023-07-13 XYenChi * config/riscv/riscv_vector.h (enum __RISCV_VXRM):Add an enum __RISCV_VXRM to help express the rounding modes. ---

Re: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM

Hmmm? I didn't get that error on selftest? my diff with your v2: $ git diff diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 12655f7fdc65..466e1aed91c7 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -8058,8 +8058,9 @@ asm_insn_p (rtx_insn *insn)

[PATCH] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

From: Yanzhang Wang gcc/ChangeLog: * config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf when enabling -mno-omit-leaf-frame-pointer (riscv_option_override): Override omit-frame-pointer. (riscv_frame_pointer_required): Save s0 for non-leaf function

[PATCH 1/4] Support Intel AVX-VNNI-INT16

From: Kong Lingling gcc/ChangeLog * common/config/i386/cpuinfo.h (get_available_features): Detect avxvnniint16. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXVNNIINT16_SET): New. (OPTION_MASK_ISA2_AVXVNNIINT16_UNSET): Ditto.

[PATCH 3/4] Support Intel SHA512

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SHA512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SHA512_SET, OPTION_MASK_ISA2_SHA512_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SHA512.

[PATCH 2/4] Support Intel SM3

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SM3. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM3_SET, OPTION_MASK_ISA2_SM3_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM3. (ix86_handle_option): Handle

[PATCH 4/4] Support Intel SM4

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detech SM4. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM4_SET, OPTION_MASK_ISA2_SM4_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM4. (ix86_handle_option): Handle

[PATCH 0/4] Support Intel Arrow Lake/Lunar Lake ISAs

Hi all, These four patches aimed to add Intel Arrow Lake/Lunar Lake instructions, including AVX-VNNI-INT16, SM3, SHA512 and SM4. The information is based on newly released Intel Architecture Instruction Set Extensions and Future Features. The document comes following:

<    1   2   3