Re: [PATCH] testsuite, Darwin: Add support for Mach-O function body scans.

Hi Richard, > On 5 Nov 2023, at 12:11, Richard Sandiford wrote: > > Iain Sandoe writes: >>> On 26 Oct 2023, at 21:00, Iain Sandoe wrote: >> On 26 Oct 2023, at 20:49, Richard Sandiford >> wrote: Iain Sandoe writes: > This was written before Thomas' modification to the

[PATCH] LoongArch: Optimize single-used address with -mexplicit-relocs=auto for fld/fst

fld and fst have same address mode as ld.w and st.w, so the same optimization as r14-4851 should be applied for them too. gcc/ChangeLog: * config/loongarch/loongarch.md (LD_AT_LEAST_32_BIT): New mode iterator. (ST_ANY): New mode iterator. (define_peephole2): Use

[Bug tree-optimization/112369] [14 regression] ICE when building webkit-gtk with -mavx

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112369 Richard Biener changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rguenth at gcc dot gnu.org

[PATCH] LoongArch: Disable relaxation if the assembler don't support conditional branch relaxation [PR112330]

As the commit message of r14-4674 has indicated, if the assembler does not support conditional branch relaxation, a relocation overflow may happen on conditional branches when relaxation is enabled because the number of NOP instructions inserted by the assembler will be more than the number

Re: [RFC] vect: disable multiple calls of poly simdclones

On Fri, 3 Nov 2023, Andre Vieira (lists) wrote: > Hi, > > The current codegen code to support VF's that are multiples of a simdclone > simdlen rely on BIT_FIELD_REF to create multiple input vectors. This does not > work for non-constant simdclones, so we should disable using such clones when >

[Bug tree-optimization/110223] Missed optimization vectorizing booleans comparisons

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110223 Andrew Pinski changed: What|Removed |Added See Also||https://gcc.gnu.org/bugzill

[PATCH 20/21]Arm: Add Advanced SIMD cbranch implementation

Hi All, This adds an implementation for conditional branch optab for AArch32. For e.g. void f1 () { for (int i = 0; i < N; i++) { b[i] += a[i]; if (a[i] > 0) break; } } For 128-bit vectors we generate: vcgt.s32q8, q9, #0 vpmax.u32

[PATCH 19/21]AArch64: Add optimization for vector cbranch combining SVE and Advanced SIMD

Hi All, Advanced SIMD lacks flag setting vector comparisons which SVE adds. Since machines with SVE also support Advanced SIMD we can use the SVE comparisons to perform the operation in cases where SVE codegen is allowed, but the vectorizer has decided to generate Advanced SIMD because of loop

[PATCH 21/21]Arm: Add MVE cbranch implementation

Hi All, This adds an implementation for conditional branch optab for MVE. Unfortunately MVE has rather limited operations on VPT.P0, we are missing the ability to do P0 comparisons and logical OR on P0. For that reason we can only support cbranch with 0, as for comparing to a 0 predicate we

[PATCH 18/21]AArch64: Add optimization for vector != cbranch fed into compare with 0 for Advanced SIMD

Hi All, Advanced SIMD lacks a cmpeq for vectors, and unlike compare to 0 we can't rewrite to a cmtst. This operation is however fairly common, especially now that we support early break vectorization. As such this adds a pattern to recognize the negated any comparison and transform it to an

[PATCH 17/21]AArch64: Add implementation for vector cbranch for Advanced SIMD

Hi All, This adds an implementation for conditional branch optab for AArch64. For e.g. void f1 () { for (int i = 0; i < N; i++) { b[i] += a[i]; if (a[i] > 0) break; } } For 128-bit vectors we generate: cmgtv1.4s, v1.4s, #0 umaxp v1.4s,

Re: [PATCH] [doc] middle-end/112296 - __builtin_constant_p and side-effects

On Fri, 3 Nov 2023, Joseph Myers wrote: > On Fri, 3 Nov 2023, Richard Biener wrote: > > > The following tries to clarify the __builtin_constant_p documentation, > > stating that the argument expression is not evaluated and side-effects > > are discarded. I'm struggling to find the correct terms

[PATCH 16/21]middle-end testsuite: un-xfail TSVC loops that check for exit control flow vectorization

Hi All, I didn't want these to get lost in the noise of updates. The following three tests now correctly work for targets that have an implementation of cbranch for vectors so XFAILs are conditionally removed gated on vect_early_break support. Bootstrapped Regtested on aarch64-none-linux-gnu

[PATCH 15/21]middle-end: [RFC] conditionally support forcing final edge for debugging

Hi All, What do people think about having the ability to force only the latch connected exit as the exit as a param? I.e. what's in the patch but as a param. I found this useful when debugging large example failures as it tells me where I should be looking. No hard requirement but just figured

[PATCH 14/21]middle-end: Change loop analysis from looking at at number of BB to actual cfg

Hi All, The vectorizer at the moment uses a num_bb check to check for control flow. This rejects a number of loops with no reason. Instead this patch changes it to check the destination of the exits instead. This also allows early break to work by also dropping the single_exit check.

[PATCH 13/21]middle-end: Update loop form analysis to support early break

Hi All, This sets LOOP_VINFO_EARLY_BREAKS and does some misc changes so the other patches are self contained. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * tree-vect-loop.cc (vect_analyze_loop_form): Analyse all exits.

[PATCH 12/21]middle-end: Add remaining changes to peeling and vectorizer to support early breaks

Hi All, This finishes wiring that didn't fit in any of the other patches. Essentially just adding related changes so peeling for early break works. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * tree-vect-loop-manip.cc

[PATCH 11/21]middle-end: wire through peeling changes and dominator updates after guard edge split

Hi All, This wires through the final bits to support adding the guard block between the loop and epilog. For an "inverted loop", i.e. one where an early exit was chosen as the main exit then we can never skip the scalar loop since we know we have side effects to still perform. For those cases

[PATCH 9/21]middle-end: implement vectorizable_early_exit for codegen of exit code

Hi All, This implements vectorable_early_exit which is used as the codegen part of vectorizing a gcond. For the most part it shares the majority of the code with vectorizable_comparison with addition that it needs to be able to reduce multiple resulting statements into a single one for use in

[PATCH 10/21]middle-end: implement relevancy analysis support for control flow

Hi All, This updates relevancy analysis to support marking gcond's belonging to early breaks as relevant for vectorization. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * tree-vect-stmts.cc (vect_stmt_relevant_p,

[PATCH 8/21]middle-end: update vectorizable_live_reduction with support for multiple exits and different exits

Hi All, This adds support to vectorizable_live_reduction to handle multiple exits by doing a search for which exit the live value should be materialized in. Additinally which value in the index we're after depends on whether the exit it's materialized in is an early exit or whether the loop's

[Bug tree-optimization/112296] __builtin_constant_p doesn't propagate through member functions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112296 Richard Biener changed: What|Removed |Added Status|ASSIGNED|NEW Keywords|documentation

[PATCH 7/21]middle-end: update IV update code to support early breaks and arbitrary exits

Hi All, This changes the PHI node updates to support early breaks. It has to support both the case where the loop's exit matches the normal loop exit and one where the early exit is "inverted", i.e. it's an early exit edge. In the latter case we must always restart the loop for VF iterations.

[PATCH 5/21]middle-end: update vectorizer's control update to support picking an exit other than loop latch

Hi All, As requested, the vectorizer is now free to pick it's own exit which can be different than what the loop CFG infrastucture uses. The vectorizer makes use of this to vectorize loops that it previously could not. But this means that loop control must be materialized in the block that

[PATCH 6/21]middle-end: support multiple exits in loop versioning

Hi All, This has loop versioning use the vectorizer's IV exit edge when it's available since single_exit (..) fails with multiple exits. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * tree-vect-loop-manip.cc

[PATCH 4/21]middle-end: update loop peeling code to maintain LCSSA form for early breaks

Hi All, This splits the part of the function that does peeling for loops at exits to a different function. In this new function we also peel for early breaks. Peeling for early breaks works by redirecting all early break exits to a single "early break" block and combine them and the normal exit

[PATCH 3/21]middle-end: Implement code motion and dependency analysis for early breaks

Hi All, When performing early break vectorization we need to be sure that the vector operations are safe to perform. A simple example is e.g. for (int i = 0; i < N; i++) { vect_b[i] = x + i; if (vect_a[i]*2 != x) break; vect_a[i] = x; } where the store to vect_b is not allowed

[PATCH 1/21]middle-end testsuite: Add more pragma novector to new tests

Hi All, This adds pragma GCC novector to testcases that have showed up since last regression run and due to this series detecting more. Is it ok that when it comes time to commit I can just update any new cases before committing? since this seems a cat and mouse game.. Bootstrapped Regtested on

[PATCH v6 0/21]middle-end: Support early break/return auto-vectorization

Hi All, This patch adds initial support for early break vectorization in GCC. The support is added for any target that implements a vector cbranch optab, this includes both fully masked and non-masked targets. Depending on the operation, the vectorizer may also require support for boolean mask

[Bug tree-optimization/112296] __builtin_constant_p doesn't propagate through member functions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112296 --- Comment #14 from CVS Commits --- The master branch has been updated by Richard Biener : https://gcc.gnu.org/g:442715708911ed6cc6f3785e3996a62f5ee7f21f commit r14-5143-g442715708911ed6cc6f3785e3996a62f5ee7f21f Author: Richard Biener Date:

Re: [PATCH] internal-fn: Add VCOND_MASK_LEN.

On Sun, 5 Nov 2023, Richard Sandiford wrote: > Robin Dapp writes: > >> Ah, OK. IMO it's better to keep the optab operands the same as the IFN > >> operands, even if that makes things inconsistent with vcond_mask. > >> vcond_mask isn't really a good example to follow, since the operand > >>

Re: [PATCH] explow: Avoid unnecessary alignment operations

On Sun, Nov 5, 2023 at 7:33 PM Richard Sandiford wrote: > > align_dynamic_address would output alignment operations even > for a required alignment of 1 byte. > > Tested on aarch64-linux-gnu & x86_64-linux-gnu. OK to install? OK > Richard > > > gcc/ > * explow.cc

Re: [PATCH] explow: Allow dynamic allocations after vregs

On Sun, Nov 5, 2023 at 7:32 PM Richard Sandiford wrote: > > This patch allows allocate_dynamic_stack_space to be called before > or after virtual registers have been instantiated. It uses the > same approach as allocate_stack_local, which already supported this. > > Tested on aarch64-linux-gnu &

[PATCH] rs6000, testcase: Add require-effective-target has_arch_ppc64 to pr106550_1.c

Hi, With latest trunk, case pr106550_1.c can run with failure on ppc under -m32. While, the case is testing 64bit constant building. So, "has_arch_ppc64" is required. Test pass on ppc64{,le}. BR, Jeff (Jiufu Guo) gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr106550_1.c: Add

[Bug target/112387] RISC-V: failed to SLP INT64 gather load

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112387 --- Comment #1 from JuzheZhong --- Oh. I see. with -fno-vect-cost-model, it can SLP now: https://godbolt.org/z/q5se4sd9x foo: beq a3,zero,.L8 csrra6,vlenb srlia4,a6,3 sllia3,a3,1 neg

[Bug middle-end/112403] New: `s+ (a?-1:1)` and `a?s-1:s+1` produce two different code generation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112403 Bug ID: 112403 Summary: `s+ (a?-1:1)` and `a?s-1:s+1` produce two different code generation Product: gcc Version: 14.0 Status: UNCONFIRMED Keywords:

[PATCH V2] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize

This patch adds strided load/store support on loop vectorizer depending on STMT_VINFO_STRIDED_P. Bootstrap and regression on X86 passed. Ok for trunk ? gcc/ChangeLog: * internal-fn.cc (strided_load_direct): New function. (strided_store_direct): Ditto.

Re: [PATCH V2] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize

Sorry. This is middle-end patch, sending to wrong CC lists. Forget about this patch. juzhe.zh...@rivai.ai From: Juzhe-Zhong Date: 2023-11-06 14:52 To: gcc-patches CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong Subject: [PATCH V2] VECT: Support

[Bug tree-optimization/112402] [11/12/13/14 Regression] Path splitting causes if-conversion miss

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112402 Andrew Pinski changed: What|Removed |Added Target Milestone|--- |11.5

[Bug tree-optimization/112402] New: [11/12/13/14 Regression] Path splitting causes if-conversion miss

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112402 Bug ID: 112402 Summary: [11/12/13/14 Regression] Path splitting causes if-conversion miss Product: gcc Version: 14.0 Status: UNCONFIRMED Keywords:

[PATCH V2] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize

This patch adds strided load/store support on loop vectorizer depending on STMT_VINFO_STRIDED_P. Bootstrap and regression on X86 passed. Ok for trunk ? gcc/ChangeLog: * internal-fn.cc (strided_load_direct): New function. (strided_store_direct): Ditto.

[Bug target/111889] [14 Regression] 128/256 intrins could not be used with only specifying "no-evex512, avx512vl" in function attribute

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111889 Haochen Jiang changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/111828] rs6000: Parse inline asm string to figure out it requires HTM feature or not.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111828 --- Comment #10 from CVS Commits --- The master branch has been updated by Kewen Lin : https://gcc.gnu.org/g:b2075291af8810794c7184fd125b991c2341cb1e commit r14-5142-gb2075291af8810794c7184fd125b991c2341cb1e Author: Kewen Lin Date: Mon Nov

[Bug rtl-optimization/112398] Suboptimal code generation for xor pattern on subword data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112398 Andrew Pinski changed: What|Removed |Added Status|WAITING |UNCONFIRMED Component|target

[Bug target/112398] Suboptimal code generation for xor pattern on subword data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112398 --- Comment #3 from Siarhei Volkau --- Well, let's rewrite it in that way: void neg8 (uint8_t *restrict dst, const uint8_t *restrict src) { uint8_t work = ~*src; // or *src ^ 0xff; dst[0] = (work >> 4) | (work << 4); } Wherever upper

[Bug c/112401] RISC-V: So many redundant move instructions due to subreg handling on vector mode

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112401 --- Comment #1 from JuzheZhong --- GCC ASM: subreg_to_reg_1: li a5,32 vsetvli zero,a5,e32,m8,ta,ma vle32.v v16,0(a0) vmv1r.v v8,v16 vmv1r.v v7,v17 vmv1r.v v6,v18 vmv1r.v v5,v19

[Bug c/112401] New: RISC-V: So many redundant move instructions due to subreg handling on vector mode

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112401 Bug ID: 112401 Summary: RISC-V: So many redundant move instructions due to subreg handling on vector mode Product: gcc Version: 14.0 Status: UNCONFIRMED

[Bug target/112400] VAX: ICE in fixup_reorder_chain, at cfgrtl.cc:4025, whilst building gimple_match.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112400 --- Comment #3 from Andrew Pinski --- Looks like it was introduced with r0-63993-g05dde071b32f .

[Bug target/112400] VAX: ICE in fixup_reorder_chain, at cfgrtl.cc:4025, whilst building gimple_match.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112400 --- Comment #2 from Andrew Pinski --- Patches should be posted to gcc-patches@ after reading https://gcc.gnu.org/contribute.html .

[Bug target/112400] VAX: ICE in fixup_reorder_chain, at cfgrtl.cc:4025, whilst building gimple_match.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112400 --- Comment #1 from Kalvis Duckmanton --- Created attachment 56512 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56512=edit patch proposed as solution

[Bug target/112400] New: VAX: ICE in fixup_reorder_chain, at cfgrtl.cc:4025, whilst building gimple_match.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112400 Bug ID: 112400 Summary: VAX: ICE in fixup_reorder_chain, at cfgrtl.cc:4025, whilst building gimple_match.cc Product: gcc Version: 12.2.0 Status: UNCONFIRMED

[PATCH] RISC-V: Enhance AVL propagation for complicate reduction auto-vectorization

I notice we failed to AVL propagate for reduction with more complicate situation: double foo (double *__restrict a, double *__restrict b, double *__restrict c, int n) { double result = 0; for (int i = 0; i < n; i++) result += a[i] * b[i] * c[i]; return result; } vsetvli

[Bug target/111907] ICE: in curr_insn_transform, at lra-constraints.cc:4294 unable to generate reloads for: {*andnottf3} with -mavx512f -mno-evex512

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111907 --- Comment #5 from Haochen Jiang --- BTW, it should be disabled since it will use zmm previously. foo(_Float128, _Float128): pushrbp mov rbp, rsp vmovdqa XMMWORD PTR [rbp-16], xmm0 vmovdqa XMMWORD PTR

[Bug target/111907] ICE: in curr_insn_transform, at lra-constraints.cc:4294 unable to generate reloads for: {*andnottf3} with -mavx512f -mno-evex512

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111907 --- Comment #4 from Haochen Jiang --- I guess it is caused by "*andnot3", not confirmed yet. The isa for the last constraint changed to avx512f_512, which will make the pattern disabled under -mavx512f -mno-evex512. Let me find a solution on

[PATCH-3, rs6000] Enable 16-byte by pieces move [PR111449]

Hi, The patch 2 enables 16-byte by pieces move on rs6000. This patch fixes the regression cases caused by previous patch. For sra-17/18, the long array with 4 elements can be loaded by one 16-byte by pieces move on 32-bit platform. So the array is not be constructed in LC0 and SRA optimization

[Bug tree-optimization/110755] [13 Regression] Wrong optimization of fabs on ppc64el at -O1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110755 Hans-Peter Nilsson changed: What|Removed |Added Target|powerpc64le |powerpc64le, aarch64

[PATCH-2, rs6000] Enable vector mode for by pieces equality compare [PR111449]

Hi, This patch enables vector mode for by pieces equality compare. It adds a new expand pattern - cbrnachv16qi4 and set MOVE_MAX_PIECES and COMPARE_MAX_PIECES to 16 bytes when P8 vector enabled. The compare relies both move and compare instructions, so both macro are changed. The vector

[Bug target/112393] [14 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1208 with -mavx5124fmaps -Wuninitialized

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112393 --- Comment #3 from Hongtao.liu --- Yes, should return true if d->testing_p instead of generate rtl code.

[Bug target/112393] [14 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1208 with -mavx5124fmaps -Wuninitialized

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112393 Andrew Pinski changed: What|Removed |Added See Also||https://gcc.gnu.org/bugzill

[Bug target/112280] [14 regression] ICE building libgcrypt-1.10.2 on s390 (during GIMPLE pass: ccp)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112280 Andrew Pinski changed: What|Removed |Added Keywords||ice-on-valid-code See Also|

[Bug libbacktrace/112396] "make check" should not error out, even when some checks failed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112396 Ian Lance Taylor changed: What|Removed |Added CC||ian at airs dot com --- Comment #3

[Bug c/112399] New: RISC-V: Missed AVL propagation for complicate reduction case

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112399 Bug ID: 112399 Summary: RISC-V: Missed AVL propagation for complicate reduction case Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/111889] [14 Regression] 128/256 intrins could not be used with only specifying "no-evex512, avx512vl" in function attribute

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111889 --- Comment #6 from CVS Commits --- The master branch has been updated by Haochen Jiang : https://gcc.gnu.org/g:fd5147177b9fa04943a3a55512b81f8f46ab4ac5 commit r14-5140-gfd5147177b9fa04943a3a55512b81f8f46ab4ac5 Author: Haochen Jiang Date:

[Bug debug/109676] [13/14 regression] ICE in simplify_subreg, at simplify-rtx.cc:7426 when building firefox with -O2 -march=alderlake -g since r13-3378-gf6c168f8c06047

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109676 Andrew Pinski changed: What|Removed |Added Status|ASSIGNED|RESOLVED Target Milestone|13.3

[Bug libbacktrace/112396] "make check" should not error out, even when some checks failed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112396 Eric Gallager changed: What|Removed |Added CC||egallager at gcc dot gnu.org ---

[Bug target/112280] [14 regression] ICE building libgcrypt-1.10.2 on s390 (during GIMPLE pass: ccp)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112280 Andrew Pinski changed: What|Removed |Added See Also||https://gcc.gnu.org/bugzill

[Bug target/112393] [14 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1208 with -mavx5124fmaps -Wuninitialized

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112393 Andrew Pinski changed: What|Removed |Added Target Milestone|--- |14.0 --- Comment #1 from Andrew Pinski

gcc-14-20231105 is now available

Snapshot gcc-14-20231105 is now available on https://gcc.gnu.org/pub/gcc/snapshots/14-20231105/ and on various mirrors, see http://gcc.gnu.org/mirrors.html for details. This snapshot has been generated from the GCC 14 git branch with the following options: git://gcc.gnu.org/git/gcc.git branch

[Bug tree-optimization/111792] [14 Regression] wrong code at -O3 on x86_64-linux-gnu since r14-3414-g0cfc9c953d0221

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111792 Andrew Pinski changed: What|Removed |Added Keywords||needs-bisection --- Comment #3 from

[Bug middle-end/111754] [14 Regression] ICE: in decompose, at rtl.h:2313 at -O

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111754 --- Comment #10 from Richard Sandiford --- Yeah, the problem went latent after the fix for PR111648, but the underlying problem is still there. Prathamesh is working on a fix for that. See the thread starting at

[Bug target/112398] Suboptimal code generation for xor pattern on subword data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112398 Andrew Pinski changed: What|Removed |Added Status|UNCONFIRMED |WAITING Last reconfirmed|

[Bug target/112398] Suboptimal code generation for xor pattern on subword data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112398 Andrew Pinski changed: What|Removed |Added Component|middle-end |target --- Comment #1 from Andrew

Re: [PATCH] testsuite, Darwin: Add support for Mach-O function body scans.

Iain Sandoe writes: > Hi Richard, > >> On 26 Oct 2023, at 21:00, Iain Sandoe wrote: > >>> On 26 Oct 2023, at 20:49, Richard Sandiford > wrote: >>> >>> Iain Sandoe writes: This was written before Thomas' modification to the ELF-handling to allow a config-based change for target

[Bug tree-optimization/105834] [13/14 Regression] Dead Code Elimination Regression at -O2 (trunk vs. 12.1.0)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105834 Thomas Koenig changed: What|Removed |Added See Also||https://gcc.gnu.org/bugzill

[Bug middle-end/112398] New: Suboptimal code generation for xor pattern on subword data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112398 Bug ID: 112398 Summary: Suboptimal code generation for xor pattern on subword data Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug middle-end/111754] [14 Regression] ICE: in decompose, at rtl.h:2313 at -O

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111754 --- Comment #9 from Andrew Pinski --- The ICE seems to be gone, and the generated code looks correct.

[Bug tree-optimization/109689] [14 Regression] ICE at -O1 with "-ftree-vectorize": in check_loop_closed_ssa_def, at tree-ssa-loop-manip.cc:645 since r14-301-gf2d6beb7a4ddf1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109689 Andrew Pinski changed: What|Removed |Added CC||shaohua.li at inf dot ethz.ch ---

[Bug tree-optimization/111389] [14 Regression] ICE in check_loop_closed_ssa_def, at tree-ssa-loop-manip.cc:647

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111389 Andrew Pinski changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug debug/110308] [14 Regression] ICE on audiofile-0.3.6: RTL: vartrack: Segmentation fault in mode_to_precision(machine_mode)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110308 Andrew Pinski changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug ipa/109711] [14 regression] ICE (tree check: expected class ‘type’, have ‘exceptional’ (error_mark) in verify_range, at value-range.cc:1060) when building ffmpeg-4.4.4 since r14-377-gc92b8be9b52b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109711 Andrew Pinski changed: What|Removed |Added CC||dcb314 at hotmail dot com --- Comment

[Bug tree-optimization/109696] [14 Regression] ice: tree check fail since r14-377

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109696 Andrew Pinski changed: What|Removed |Added Resolution|--- |DUPLICATE Status|NEW

[Bug tree-optimization/109696] [14 Regression] ice: tree check fail since r14-377

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109696 Andrew Pinski changed: What|Removed |Added Keywords||needs-bisection --- Comment #2 from

[Bug tree-optimization/111572] [14 Regression] Wrong code at -O2 on x86_64-linux-gnu since r14-301-gf2d6beb7a4d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111572 Andrew Pinski changed: What|Removed |Added Keywords||needs-bisection --- Comment #5 from

Re: [PATCH] Testsuite, i386: Mark test as requiring dfp

On Nov 5, 2023, at 12:33 PM, FX Coudert wrote: > > kind ping for this easy patch > > >> Le 30 oct. 2023 à 15:19, FX Coudert a écrit : >> >> Hi, >> >> The test is currently failing on x86_64-apple-darwin with "decimal >> floating-point not supported for this target”. >> Marking the test as

Re: [PATCH] testsuite: check for and use -mno-strict-align where needed

On Oct 19, 2023, at 8:16 PM, Alexandre Oliva wrote: > > On Mar 10, 2021, Alexandre Oliva wrote: > >> ppc configurations that have -mstrict-align enabled by default fail >> gcc.dg/strlenopt-80.c, because some memcpy calls don't get turned into >> MEM_REFs, which defeats the tested-for strlen

Re: [PATCH 1/2] testsuite: Add and use thread_fence effective-target

On Oct 2, 2023, at 1:24 AM, Christophe Lyon wrote: > > ping? > > On Sun, 10 Sept 2023 at 21:31, Christophe Lyon > wrote: > Some targets like arm-eabi with newlib and default settings rely on > __sync_synchronize() to ensure synchronization. Newlib does not > implement it by default, to make

[Bug libstdc++/112397] New: Two persistent libstdc++ test failures on x86_64-apple-darwin

gned long, s td::nothrow_t const&)' from file '/Users/fx/ibin-20231105/x86_64-apple-darwin21/./libstdc++-v3/src/.libs/libstdc++.a(new_opvnt.o)' m eans the weak symbol cannot be overridden at runtime. This was likely caused by different translation units being compiled with diff erent visibility

Re: testsuite: introduce hostedlib effective target

On Nov 1, 2023, at 6:11 PM, Alexandre Oliva wrote: > > Several C++ tests fail with --disable-hosted-libstdcxx, whether > because stdc++ext gets linked in despite not being built, because > standard headers are included but that are unavailable in this mode, > or because headers are (mistakenly?)

[Bug libbacktrace/112396] "make check" should not error out, even when some checks failed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112396 --- Comment #1 from Andrew Pinski --- https://gcc.gnu.org/install/test.html Even mentions -k option for a long time.

Re: [PATCH] Testsuite, i386: Mark test as requiring dfp

Hi FX > On 5 Nov 2023, at 10:33, FX Coudert wrote: > > kind ping for this easy patch IMO adding feature tests for features required by a test falls into the “obvious” category, Iain > > >> Le 30 oct. 2023 à 15:19, FX Coudert a écrit : >> >> Hi, >> >> The test is currently failing on

Re: [PATCH] Testsuite, i386: Mark test as requiring dfp

kind ping for this easy patch > Le 30 oct. 2023 à 15:19, FX Coudert a écrit : > > Hi, > > The test is currently failing on x86_64-apple-darwin with "decimal > floating-point not supported for this target”. > Marking the test as requiring dfp fixes the issue. > > OK to push? > > FX >

[Bug libbacktrace/112396] New: "make check" should not error out, even when some checks failed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112396 Bug ID: 112396 Summary: "make check" should not error out, even when some checks failed Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

Re: [PATCH] internal-fn: Add VCOND_MASK_LEN.

Robin Dapp writes: >> Ah, OK. IMO it's better to keep the optab operands the same as the IFN >> operands, even if that makes things inconsistent with vcond_mask. >> vcond_mask isn't really a good example to follow, since the operand >> order is not only inconsistent with the IFN, it's also

Re: [PATCH] testsuite: Force use of -c when precompiling headers

On Oct 27, 2023, at 8:11 AM, Christophe Lyon wrote: > > In some configurations of our validation setup, we always call the > compiler with -Wl,-rpath=XXX, which instructs the driver to invoke the > linker if none of -c, -S or -E is used. > > This happens to be the case in the PCH tests, where

Re: [1/3] Add support for target_version attribute

Andrew Carlotti writes: > On Thu, Oct 26, 2023 at 07:41:09PM +0100, Richard Sandiford wrote: >> Andrew Carlotti writes: >> > This patch adds support for the "target_version" attribute to the middle >> > end and the C++ frontend, which will be used to implement function >> > multiversioning in

[committed] i386: Add LEGACY_INDEX_REG register class.

Also rename LEGACY_REGS to LEGACY_GENERAL_REGS. gcc/ChangeLog: * config/i386/i386.h (enum reg_class): Add LEGACY_INDEX_REGS. Rename LEGACY_REGS to LEGACY_GENERAL_REGS. (REG_CLASS_NAMES): Ditto. (REG_CLASS_CONTENTS): Ditto. * config/i386/constraints.md ("R"): Update for

Re: [PATCH] Remove unnecessary "& 1" in year_month_day_last::day()

On Sun, Nov 5, 2023 at 9:13 AM Cassio Neri wrote: > > I could not find any entry in gcc's bugzilla for that. Perhaps my search > wasn't good enough. I filed https://gcc.gnu.org/PR112395 with a first attempt at the patch (will double check it soon). Thanks, Andrew > > > On Sun, 5 Nov 2023 at

[Bug tree-optimization/112395] `CST1| (x & CST0)` -> `0x1e | x` iff `x` known zero bits outside of CST1 is known to be 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112395 Andrew Pinski changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |pinskia at gcc dot gnu.org

[Bug tree-optimization/112395] New: `CST1| (x & CST0)` -> `0x1e | x` iff `x` known zero bits outside of CST1 is known to be 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112395 Bug ID: 112395 Summary: `CST1| (x & CST0)` -> `0x1e | x` iff `x` known zero bits outside of CST1 is known to be 0 Product: gcc Version: 14.0 Status: UNCONFIRMED

[Bug rtl-optimization/112380] [14 regression] ICE when building Mesa (in combine, internal compiler error: in simplify_subreg) since r14-2526-g8911879415d6c2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112380 Roger Sayle changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |roger at nextmovesoftware dot com

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