gcc-12-20240912 is now available

2024-09-12 Thread GCC Administrator via Gcc
Snapshot gcc-12-20240912 is now available on https://gcc.gnu.org/pub/gcc/snapshots/12-20240912/ and on various mirrors, see https://gcc.gnu.org/mirrors.html for details. This snapshot has been generated from the GCC 12 git branch with the following options: git://gcc.gnu.org/git/gcc.git branch

Sourceware Open Office Friday and Cauldron Monday

2024-09-12 Thread Mark Wielaard
We'll have our regular Sourceware Open Office this Friday Sep 13, 16:00 UTC Using #overseers on irc.libera.chat To get the right time in your local timezone: $ date -d "Fri Sep 13 16:00 UTC 2024" Then at the Cauldron https://gcc.gnu.org/wiki/cauldron2024 in Prague on Monday at 11:00 local time we

[CAULDRON] Topics for the Toolchain and Linux kernel BoF

2024-09-12 Thread Jose E. Marchesi via Gcc
Hello people! This year we will be having a kernel BoF at Cauldron. It is scheduled for Saturday from 15:30 to 16:30. There will be several kernel maintainers and hackers in attendance, and the goal of the BoF is to discuss and collect feedback about several toolchain-related issues that are o

Re: Proposed new pass to optimise mode register assignments

2024-09-12 Thread Jeff Law via Gcc
On 9/12/24 8:22 AM, Richard Sandiford wrote: This has recently come up in the RISC-V space due to needing VXRM assignments so that we can utilize the vaaddu add-with-averaging instructions.Placement of VXRM mode switches looks optimal from an LCM standpoint, but speculation can measurabl

Re: Proposed new pass to optimise mode register assignments

2024-09-12 Thread Richard Sandiford via Gcc
Jeff Law writes: > On 9/7/24 1:09 AM, Richard Biener wrote: >> >> >>> Am 06.09.2024 um 17:38 schrieb Andrew Carlotti : >>> >>> Hi, >>> >>> I'm working on optimising assignments to the AArch64 Floating-point Mode >>> Register (FPMR), as part of our FP8 enablement work. Claudio has already >>> i

Re: Late combine & mode switch

2024-09-12 Thread Richard Sandiford via Gcc
Sorry for the slow response. Xi Ruoyao writes: > Hi Richard, > > When I hack the LoongArch backend I notice something like > > slli.d $r4, $r4, 2 > add.w $r4, $r4, $r5 > > Or > > (set (reg:DI 4) (ashift:DI (reg:DI 4) (const_int 2)) > (set (reg:DI 4) > (sign_extend:DI (add:SI (reg:SI 4) (reg:

Re: Referencing a register in different modes

2024-09-12 Thread Stefan Schulze Frielinghaus via Gcc
On Fri, Aug 09, 2024 at 09:49:03AM +0200, Stefan Schulze Frielinghaus wrote: > On Thu, Aug 08, 2024 at 01:56:48PM -0600, Jeff Law wrote: > > > I haven't tested it extensively but it triggers at least for the current > > > case. > > > I would have loved to also print the insn but couldn't figure ou