Re: [PATCH 0/2] RISC-V: Add ldr/str instruction for T-HEAD.

2021-07-10 Thread ALO via Gcc-patches
Hi, Ping. @Jim @kito — Jojo 在 2021年7月9日 +0800 AM9:30,ALO ,写道: > Hi, > Ping. > > — Jojo > 在 2021年6月29日 +0800 PM4:11,Jojo R ,写道: > > T-HEAD extends some customized ISAs for Cores. > > The patches support ldr/str insns, it likes arm's LDR insn, the > > memory model is a base

Re: [PATCH 0/2] RISC-V: Add ldr/str instruction for T-HEAD.

2021-07-08 Thread ALO via Gcc-patches
Hi, Ping. — Jojo 在 2021年6月29日 +0800 PM4:11,Jojo R ,写道: > T-HEAD extends some customized ISAs for Cores. > The patches support ldr/str insns, it likes arm's LDR insn, the > memory model is a base register indexed by (optionally scaled) register.

__fp16 is ambiguous error in C++

2021-06-24 Thread ALO via Gcc
#include __fp16 foo (__fp16 a, __fp16 b) { return a + std::exp(b); } compiler options: = riscv64-unknown-linux-gnu-g++ foo.c -march=rv64gc_zfh -mabi=lp64 error: == foo.c: In function '__fp16 foo(__fp16, __fp16)': foo.c:6:23: error: call of overloaded 'exp(__fp16&)' is