It is indeed caused by wrong DF information, which is caused by a
wrong fix for bug PR32339.
More discussion is at https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63156.
thanks a lot
Guozhi Wei
On Tue, Sep 9, 2014 at 5:31 PM, Jan Hubicka wrote:
>> On 09/03/14 02:35, Steven Bosscher wrote:
>> >On We
On Wed, Sep 3, 2014 at 1:29 AM, Steven Bosscher wrote:
> On Wed, Sep 3, 2014 at 1:35 AM, Carrot Wei wrote:
>> 1. It is well known that register renaming is a big help to register
>> allocation, but in gcc's backend, the web pass is far before RA, there
>> are about 20 pa
OINC expressions. I will debug it more.
thanks
Guozhi Wei
On Tue, Sep 2, 2014 at 4:35 PM, Carrot Wei wrote:
> Hi
>
> I have following questions about web (pseudo register renaming) pass:
>
> 1. It is well known that register renaming is a big help to register
> allocation, but in gcc&#
Hi
I have following questions about web (pseudo register renaming) pass:
1. It is well known that register renaming is a big help to register
allocation, but in gcc's backend, the web pass is far before RA, there
are about 20 passes between them. Does it mean register renaming can
also heavily be
constraint to movdi_internal64 to
load 0 to VSX register.
thanks
Guozhi Wei
On Tue, Aug 5, 2014 at 1:38 PM, Segher Boessenkool
wrote:
> On Tue, Aug 05, 2014 at 01:32:00PM +0930, Alan Modra wrote:
>> On Mon, Aug 04, 2014 at 05:54:04PM -0700, Carrot Wei wrote:
>> > Another problem is in
On Mon, Aug 4, 2014 at 9:02 PM, Alan Modra wrote:
> On Mon, Aug 04, 2014 at 05:54:04PM -0700, Carrot Wei wrote:
>> Another problem is in the definition of insn pattern "*movdi_internal64".
>>
>> (define_insn "*movdi_internal64"
>> [(set (match_ope
4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])
The predicates of this insn pattern allow the moving of an integer to
VSX register, but there is no constraint allow this case. Can this
cause problem in reload?
thanks
Guozhi Wei
On Mon, Jul 28, 2014 at 5:49 PM, Carrot Wei wrote:
> Hi Vlad
>
> When
Hi Vlad
When I use ppc64 gcc4.9 to compile an internal application I got an
ICE due to an invalid instruction generated by reload.
Before IRA, I have following insns:
(insn 139 136 581 10 (set (reg:DI 567)
(const_int 0 [0])) ./strings/stringpiece.h:205 discrim 1 520
{*movdi_internal64}
On Wed, Jul 17, 2013 at 6:01 PM, David Edelsohn wrote:
> On Wed, Jul 17, 2013 at 7:27 PM, Carrot Wei wrote:
>> Hi
>>
>> When I tried to build 444.namd with options "-O2 -m64 -mvsx
>> -mcpu=power7", I can see vsx instructions are actually used, there are
>&
Hi
When I tried to build 444.namd with options "-O2 -m64 -mvsx
-mcpu=power7", I can see vsx instructions are actually used, there are
many xs- started instructions, but none of them use high registers
[vsr32 -vsr63], does anybody know the reason?
One example is function calc_pair_energy_fullelect
You are right, it's my fault.
thanks a lot
Carrot
On Fri, Mar 29, 2013 at 6:33 PM, Alan Modra wrote:
> On Fri, Mar 29, 2013 at 04:58:50PM -0700, Carrot Wei wrote:
>> /trunkbin/bin/gcc -c -o rtl.o -DSPEC_CPU -DNDEBUG -I. -O2
>> -DSPEC_CPU_LP64 -m32rtl.c
>
>
Hi
I built a native power gcc, and used it to build 403.gcc in SPEC2006,
I got the following error when I specify -m32
In file included from rtl.c:188:0:
machmode.def:79:1: warning: left shift count >= width of type [enabled
by default]
DEF_MACHMODE (SImode, "SI", MODE_INT, BITS_PER_UNIT*4, 4, 4
the cse/gcse that removes the two load insns. For ARM,
> GOT address is loaded into sl reg.
>
> So simplify_GOT should precede register allocation. Otherwise compiler
> cannot exploit the relaxed register. I suggest the simplify_GOT is
> integrated into expand_pass, where we can con
at 8:10 PM, Andrew Haley wrote:
>> On 28/03/10 15:45, Carrot Wei wrote:
>>> Hi
>>>
>>> The detailed description of the optimization is at
>>> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43129. This is an ARM
>>> specific optimization.
>>>
&g
Hi
The detailed description of the optimization is at
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43129. This is an ARM
specific optimization.
This optimization uses one less register (the register hold the GOT
base), to get this beneficial the ideal place for it should be before
register allocat
Could anybody help to review the small patch
http://gcc.gnu.org/ml/gcc-patches/2010-01/msg00531.html
thanks
Guozhi
On Sat, Jan 9, 2010 at 7:25 PM, Carrot Wei wrote:
> OK, I filed a bug to trace it.
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42671
>
> thanks
> Guozhi
>
>
OK, I filed a bug to trace it.
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42671
thanks
Guozhi
On Thu, Jan 7, 2010 at 6:23 PM, Richard Earnshaw wrote:
>
> On Wed, 2010-01-06 at 18:26 +, Paul Brook wrote:
>> On Wednesday 06 January 2010, Carrot Wei wrote:
>> > So th
2010 at 2:26 AM, Paul Brook wrote:
> On Wednesday 06 January 2010, Carrot Wei wrote:
>> So thumb2 can also use the instructions similar to thumb1, right? It
>> potentially has better performance and smaller code size.
>
> Technically yes, however in ARMv7 the relevant inst
So thumb2 can also use the instructions similar to thumb1, right? It
potentially has better performance and smaller code size.
thanks
Carrot
On Tue, Jan 5, 2010 at 7:06 PM, Richard Earnshaw wrote:
>
> On Tue, 2010-01-05 at 15:42 +0800, Carrot Wei wrote:
>> Hi
>&
Hi
In function arm_load_pic_register in file arm.c there are following code:
if (TARGET_ARM)
{
...
}
else if (TARGET_THUMB2)
{
/* Thumb-2 only allows very limited access to the PC. Calculate the
address in a temporary reg
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