>
> From: Kyrylo Tkachov
> Sent: Friday, December 11, 2020 11:23 AM
> To: Dennis Zhang; gcc-patches@gcc.gnu.org
> Cc: nd; Richard Earnshaw; Marcus Shawcroft; Richard Sandiford
> Subject: RE: [backport gcc-10][AArch64] ACLE bf16 convert
>
> > -Original
Hi Kyrylo,
>
> From: Kyrylo Tkachov
> Sent: Friday, December 11, 2020 11:58 AM
> To: Dennis Zhang; gcc-patches@gcc.gnu.org
> Cc: nd; Richard Earnshaw; Marcus Shawcroft; Richard Sandiford
> Subject: RE: [backport gcc-10][AArch64] ACLE bf16 get
>
> >
Hi Christophe,
> From: Christophe Lyon
> Sent: Monday, November 9, 2020 1:38 PM
> To: Dennis Zhang
> Cc: Kyrylo Tkachov; gcc-patches@gcc.gnu.org; Richard Earnshaw; nd; Ramana
> Radhakrishnan
> Subject: Re: [PATCH][Arm] Auto-vectorization for MVE: vsub
>
> Hi,
>
> I have just noticed that the
This patch fixes a typo reported at
https://gcc.gnu.org/pipermail/gcc-patches/2020-November/558478.html
gcc/testsuite/
* gcc.target/arm/simd/mve-vsub_1.c: Fix typo.
Remove needless dg-additional-options.
Cheers,
Dennisdiff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vsub_1.c
Hi all,
This patch backports the commit 3553c658533e430b232997bdfd97faf6606fb102.
The original is approved at
https://gcc.gnu.org/pipermail/gcc-patches/2020-November/557871.html
There is a change to remove FPCR-reading flag for builtin declaration since
it's not supported in gcc-10.
Another
Hi all,
This patch backports the commit f7d6961126a7f06c8089d8a58bd21be43bc16806.
The original is approved at
https://gcc.gnu.org/pipermail/gcc-patches/2020-November/557859.html
The only change is to remove FPCR-reading flags for builtin definition since
it's not supported in gcc-10.
Regtested
On 11/3/20 2:05 PM, Richard Sandiford wrote:
Dennis Zhang writes:
Hi Richard,
On 10/30/20 2:07 PM, Richard Sandiford wrote:
Dennis Zhang writes:
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def
b/gcc/config/aarch64/aarch64-simd-builtins.def
index 332a0b6b1ea..39ebb776d1d 100644
On 11/2/20 7:05 PM, Richard Sandiford wrote:
Dennis Zhang writes:
Hi Richard,
On 10/29/20 5:48 PM, Richard Sandiford wrote:
Dennis Zhang writes:
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def
b/gcc/config/aarch64/aarch64-simd-builtins.def
index 5bc596dbffc..b68c3ca7f4b 100644
Hi Richard,
On 10/30/20 2:07 PM, Richard Sandiford wrote:
Dennis Zhang writes:
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def
b/gcc/config/aarch64/aarch64-simd-builtins.def
index 332a0b6b1ea..39ebb776d1d 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++
Hi Richard,
On 10/29/20 5:48 PM, Richard Sandiford wrote:
Dennis Zhang writes:
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def
b/gcc/config/aarch64/aarch64-simd-builtins.def
index 5bc596dbffc..b68c3ca7f4b 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++
Hi all,
This patch implements ACLE intrinsics vget_low_bf16 and vget_high_bf16 to
extract lower or higher half from a bfloat16x8 vector.
The vget_high_bf16 is done by 'dup' instruction. The vget_low_bf16 could be
done by a 'dup' or 'mov', or it's mostly optimized out by just using the lower
Hi all,
This patch enables intrinsics to convert BFloat16 scalar and vector operands to
Float32 modes.
The intrinsics are implemented by shifting each BFloat16 item 16 bits to left
using shl/shll/shll2 instructions.
Intrinsics are documented at
Hi Kyrylo,
>
> From: Kyrylo Tkachov
> Sent: Thursday, October 22, 2020 9:40 AM
> To: Dennis Zhang; gcc-patches@gcc.gnu.org
> Cc: nd; Richard Earnshaw; Ramana Radhakrishnan
> Subject: RE: [PATCH][Arm] Auto-vectorization for MVE: vsub
>
> Hi Dennis,
>
> >
Ping: https://gcc.gnu.org/pipermail/gcc-patches/2020-October/555646.html
Thanks
From: Dennis Zhang
Sent: Tuesday, October 6, 2020 5:46 PM
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov; nd; Richard Earnshaw; Ramana Radhakrishnan
Subject: Re: [PATCH][Arm]
Hi Kyrylo,
>
> From: Kyrylo Tkachov
> Sent: Wednesday, October 14, 2020 10:15 AM
> To: Dennis Zhang; gcc-patches@gcc.gnu.org
> Cc: nd; Richard Earnshaw; Ramana Radhakrishnan
> Subject: RE: [PATCH][Arm] Auto-vectorization for MVE: vmin/vmax
>
> Hi Dennis,
Hi kyrylo,
>
> From: Kyrylo Tkachov
> Sent: Wednesday, October 14, 2020 10:14 AM
> To: Dennis Zhang; gcc-patches@gcc.gnu.org
> Cc: nd; Richard Earnshaw; Ramana Radhakrishnan
> Subject: RE: [PATCH][Arm] Auto-vectorization for MVE: vmul
>
> Hi Dennis,
>
>
Hi Christophe,
On 12/10/2020 12:40, Christophe Lyon wrote:
Hi,
On Thu, 8 Oct 2020 at 16:22, Christophe Lyon wrote:
On Thu, 8 Oct 2020 at 16:08, Dennis Zhang wrote:
Hi Christophe,
On 08/10/2020 14:14, Christophe Lyon wrote:
Hi,
On Tue, 6 Oct 2020 at 15:37, Dennis Zhang via Gcc
Hi Christophe,
On 08/10/2020 14:14, Christophe Lyon wrote:
Hi,
On Tue, 6 Oct 2020 at 15:37, Dennis Zhang via Gcc-patches
wrote:
On 9/16/20 4:00 PM, Dennis Zhang wrote:
Hi all,
This patch enables SIMD modes for MVE auto-vectorization.
In this patch, the integer and float MVE SIMD modes
Hi all,
This patch enables MVE vmin/vmax instructions for auto-vectorization.
MVE target is included in expander smin3, umin3, smax3
and umax3 for vectorization.
Related insns for vmin/vmax in mve.md are modified to use smin, umin,
smax and umax expressions instead of unspec to support the
Hi all,
This patch enables MVE vmul instructions for auto-vectorization.
It includes MVE in expander mul3 to enable vectorization for MVE
and modifies related vmul insns to support the expander by using 'mult'
instead of unspec.
The mul3 for vectorization in vec-common.md uses mode iterator
Hi all,
On 8/17/20 6:41 PM, Dennis Zhang wrote:
>
> Hi all,
>
> This patch enables MVE vsub instructions for auto-vectorization.
> It adds RTL templates for MVE vsub instructions using 'minus' instead of
> unspec expression to make the instructions recognizable for vectorization.
> MVE target
On 9/16/20 4:00 PM, Dennis Zhang wrote:
> Hi all,
>
> This patch enables SIMD modes for MVE auto-vectorization.
> In this patch, the integer and float MVE SIMD modes are returned by
> arm_preferred_simd_mode (TARGET_VECTORIZE_PREFERRED_SIMD_MODE hook) when
> MVE or MVE_FLOAT is enabled.
> Then
22 matches
Mail list logo
