Re: [PATCH v3, rs6000] Implement mffscrni pattern

Hi Segher, Thanks for your advice. Please see my explanation below. On 22/12/2021 上午 1:05, Segher Boessenkool wrote: > Hi! > > On Tue, Dec 21, 2021 at 04:08:06PM +0800, HAO CHEN GUI wrote: >> This patch defines a pattern for mffscrni. If the RN is a constant, it can >> call >>

[PATCH, rs6000] Fix ICE on expand bcd__ [PR100736]

Hi, This patch fixes the ICE in PR100736. It adds a reverse condition comparison when the condition code can be reversed and finite-math-only is set. Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Is this okay for trunk? Any recommendations? Thanks a lot.

[PATCH v3, rs6000] Implement mffscrni pattern

Hi, I modified the patch according to reviewers' advice. This patch defines a pattern for mffscrni. If the RN is a constant, it can call gen_rs6000_mffscrni directly. The "rs6000-builtin-new.def" defines prototype for builtin arguments. The pattern "rs6000_set_fpscr_rn" is then broken as

[PATCH, rs6000] Implement mffscrni pattern

Hi, I modified the patch according to David and Segher's advice. This patch defines a pattern for mffscrni. If the RN is a constant, it can call gen_rs6000_mffscrni directly. The "rs6000-builtin-new.def" defines prototype for builtin arguments. The pattern "rs6000_set_fpscr_rn" is then

[PATCH, rs6000] Implement mffscrni pattern

Hi, This patch defines a pattern for mffscrni. If the RN is a constant, it can call gen_rs6000_mffscrni directly. The "rs6000-builtin-new.def" defines prototype for builtin arguments. The pattern "rs6000_set_fpscr_rn" is then broken as the mode of its argument is DI while its corresponding

[PATCH, rs6000] new split pattern for TI to V1TI move [PR103124]

Hi, This patch defines a new split pattern for TI to V1TI move. The pattern concatenates two subreg:DI of a TI to a V2DI. With the pattern, the subreg pass can do register split for TI when there is a TI to V1TI move. The patch optimizes one unnecessary "mr" out on P9. The new test case

Re: [PATCH, rs6000] new split pattern for TI to V1TI move [PR103124]

Hi Segher, Thanks for your advice. Please see my comments. On 14/12/2021 上午 6:59, Segher Boessenkool wrote: > Hi! > > On Mon, Dec 13, 2021 at 05:22:06PM -0500, David Edelsohn wrote: >> On Sun, Dec 12, 2021 at 10:00 PM HAO CHEN GUI wrote: >>> --- a/gcc/config/rs6000/vsx.md >>> +++

[PATCH, rs6000] new split pattern for TI to V1TI move [PR103124]

Hi, This patch defines a new split pattern for TI to V1TI move. The pattern concatenates two subreg:DI of a TI to a V2DI, then move the V2DI to V1TI. With the pattern, the subreg pass can do register split for TI when there is a TI to V1TI move. The patch optimizes one unnecessary "mr" out

[PATCH] Modify combine pattern by a pseudo AND with its nonzero bits [PR93453]

Hi, This patch modifies the combine pattern with a helper - change_pseudo_and_mask when recog fails. The helper converts a single pseudo to the pseudo AND with a mask if the outer operator is IOR/XOR/PLUS and the inner operator is ASHIFT/LSHIFTRT/AND. The conversion helps on shift + ior

Re: [PATCH] Modify combine pattern by a pseudo AND with its nonzero bits [PR93453]

Kewen, Many thanks for your comments. On 2/12/2021 上午 10:21, Kewen.Lin wrote: > Hi Haochen, > > on 2021/12/1 下午5:01, HAO CHEN GUI via Gcc-patches wrote: >> Hi, >> This patch modifies the combine pattern with a helper - >> change_pseudo_and_mask when recog fa

[PATCH] Modify combine pattern by a pseudo AND with its nonzero bits [PR93453]

Hi, This patch modifies the combine pattern with a helper - change_pseudo_and_mask when recog fails. The helper converts a single pseudo to the pseudo AND with a mask if the outer operator is IOR/XOR/PLUS and the inner operator is ASHIFT/LSHIFTRT/AND. The conversion helps match shift + ior

Re: [PATCH] Modify combine pattern by anding a pseudo with its nonzero bits

Hi Segher,    Thanks for your review. Please see my comments. On 1/12/2021 上午 2:11, Segher Boessenkool wrote: > Hi! > > On Tue, Nov 30, 2021 at 04:46:34PM +0800, HAO CHEN GUI wrote: >>     This patch modifies the combine pattern with a helper - >> change_pseudo_and_mask when recog fails. The

[PATCH] Modify combine pattern by anding a pseudo with its nonzero bits

Hi,     This patch modifies the combine pattern with a helper - change_pseudo_and_mask when recog fails. The helper converts a single pseudo to the pseudo and with a mask if the outer operator is IOR/XOR/PLUS and the inner operator is ASHIFT/LSHIFTRT/AND. The conversion helps match shift + ior

Re: [PATCH, rs6000] optimization for vec_reve builtin [PR100868]

Thanks for your review. Committed as r12-5463. On 22/11/2021 上午 10:56, David Edelsohn wrote: > On Wed, Nov 17, 2021 at 3:28 AM HAO CHEN GUI wrote: >> Hi, >> >> The patch optimized for vec_reve builtin on rs6000. For V2DI and V2DF, it >> is implemented by xxswapd on all targets. For V16QI,

Re: [PATCH 0/3] Add zero cycle move support

Bill and David,     Currently, the absolute jump table is not by default enabled. It can be enabled by undocumented option "-mno-relative-jumptables". If the target supports named sections (have_named_sections), the feature can be enabled. We plan to enable the future by default in GCC12 and

[PATCH, rs6000] optimization for vec_reve builtin [PR100868]

Hi,   The patch optimized for vec_reve builtin on rs6000. For V2DI and V2DF, it is implemented by xxswapd on all targets. For V16QI, V8HI, V4SI and V4SF, it is implemented by quadword byte reverse plus halfword/word byte reverse when p9_vector is set.   Bootstrapped and tested on

Re: [PATCH, rs6000] Optimization for vec_xl_sext

Bill,     Sorry, I mixed up the patches. There is one vec_reve patch which hasn't gotten approval for a long time. I will re-send it.  Thanks a lot. On 16/11/2021 下午 9:10, Bill Schmidt wrote: > Hi Hao Chen, > > I don't understand.  This patch was already approved and you committed it. > :-) I

[PATCH, rs6000] Optimization for vec_xl_sext

Hi,    The patch optimizes the code generation for vec_xl_sext builtin. Now all the  sign extensions are done on VSX registers directly.    Bootstrapped and tested on powerpc64le-linux with no regressions. Is this  okay for trunk? Any recommendations? Thanks a lot. ChangeLog 2021-11-16 Haochen

Re: [PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

David,   Thanks for your comments. I refined it according to your advice. ChangeLog 2021-11-01 Haochen Gui gcc/     * config/rs6000/rs6000-call.c (rs6000_gimple_fold_builtin): Disable     gimple fold for VSX_BUILTIN_XVMINDP, ALTIVEC_BUILTIN_VMINFP,     VSX_BUILTIN_XVMAXDP,

Re: [PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

David,     My patch file was broken. I am sorry for it.  Here is the correct one. Thanks a lot. ChangeLog 2021-11-01 Haochen Gui gcc/     * config/rs6000/rs6000-call.c (rs6000_gimple_fold_builtin): Disable     gimple fold for VSX_BUILTIN_XVMINDP, ALTIVEC_BUILTIN_VMINFP,    

[PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

Hi,   This patch disables gimple folding for VSX_BUILTIN_XVMINDP, VSX_BUILTIN_XVMAXDP, ALTIVEC_BUILTIN_VMINFP and  ALTIVEC_BUILTIN_VMAXFP when  fast-math is not set.  With the gimple folding is enabled, the four built-ins will be implemented by c-type instructions - xs[min|max]cdp on P9 and P10

Re: [PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

On 21/10/2021 上午 12:19, Segher Boessenkool wrote: > Hi! > > On Wed, Oct 20, 2021 at 05:04:56PM +0800, HAO CHEN GUI wrote: >> This patch disables gimple folding for float or double vec_min/max when  >> fast-math is not set. It makes vec_min/max conform with the guide. >> >> Bootstrapped and 

[PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

Hi, This patch disables gimple folding for float or double vec_min/max when  fast-math is not set. It makes vec_min/max conform with the guide. Bootstrapped and tested on powerpc64le-linux with no regressions. Is this okay  for trunk? Any recommendations? Thanks a lot.   I refined the patch

Re: PATCH, rs6000] Optimization for vec_xl_sext

Committed as r12-4494. Thanks to all of you. Gui Haochen On 15/10/2021 上午 2:53, David Edelsohn wrote: On Thu, Oct 14, 2021 at 2:17 AM HAO CHEN GUI wrote: Hi, The patch optimizes the code generation for vec_xl_sext builtin. Now all the sign extensions are done on VSX registers directly.

Re: [PATCH, rs6000] punish reload of lfiwzx when loading an int variable [PR102169, PR102146]

On 14/10/2021 上午 8:12, Segher Boessenkool wrote: On Wed, Sep 29, 2021 at 04:32:19PM +0800, HAO CHEN GUI wrote:   The patch punishes reload of alternative pair of "d, Z" for movsi_internal1. The reload occurs if 'Z' doesn't match and generates an additional insn. So the memory reload should

PATCH, rs6000] Optimization for vec_xl_sext

Hi,   The patch optimizes the code generation for vec_xl_sext builtin. Now all the sign extensions are done on VSX registers directly.   Bootstrapped and tested on powerpc64le-linux with no regressions. Is this okay for trunk? Any recommendations? Thanks a lot.   I refined the patch

Re: [PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

the other a quiet NaN. Otherwise it is either xor y, canonicalized (this means results might differ among implementations). When either xor yis a signalingNaN, then the result is according to 6.2. Thanks again. Gui Haochen On 12/10/2021 下午 5:57, Richard Biener wrote: On Tue, Oct 12, 2021 at

Re: [PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

ue, Oct 12, 2021 at 10:59 AM HAO CHEN GUI via Gcc-patches wrote: Hi, This patch disables gimple folding for float or double vec_min/max when fast-math is not set. It makes vec_min/max conform with the guide. Bootstrapped and tested on powerpc64le-linux with no regressions. Is this okay

[PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

Hi,    This patch disables gimple folding for float or double vec_min/max when fast-math is not set. It makes vec_min/max conform with the guide. Bootstrapped and tested on powerpc64le-linux with no regressions. Is this okay  for trunk? Any recommendations? Thanks a lot.    I re-send the

[PATCH, rs6000] Optimization for vec_xl_sext

Hi,    The patch optimized the code generation for vec_xl_sext builtin. Now all the  sign extensions are done on VSX registers directly.    Bootstrapped and tested on powerpc64le-linux with no regressions. Is this  okay for trunk? Any recommendations? Thanks a lot. ChangeLog 2021-10-11

Ping^1 [PATCH, rs6000] punish reload of lfiwzx when loading an int variable [PR102169, PR102146]

Hi,     Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2021-September/580479.html Thanks On 29/9/2021 下午 4:32, HAO CHEN GUI wrote: Hi,   The patch punishes reload of alternative pair of "d, Z" for movsi_internal1. The reload occurs if 'Z' doesn't match and generates an

Ping^1 [PATCH, rs6000] optimization for vec_reve builtin [PR100868]

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2021-September/579038.html Thanks On 8/9/2021 下午 2:42, HAO CHEN GUI wrote: Hi,   The patch optimized for vec_reve builtin on rs6000. For V2DI and V2DF, it is implemented by xxswapd on all targets. For V16QI, V8HI, V4SI

PING^3 [PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

Hi,     Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2021-August/578162.html Thanks On 22/9/2021 下午 2:52, HAO CHEN GUI wrote: Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2021-August/578162.html Thanks On 6/9/2021 下午 2:01, HAO CHEN GUI wrote:

[PATCH, rs6000] punish reload of lfiwzx when loading an int variable [PR102169, PR102146]

Hi,   The patch punishes reload of alternative pair of "d, Z" for movsi_internal1. The reload occurs if 'Z' doesn't match and generates an additional insn. So the memory reload should be punished.   Bootstrapped and tested on powerpc64le-linux with no regressions. Is this  okay for trunk? Any 

PING^2 [PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2021-August/578162.html Thanks On 6/9/2021 下午 2:01, HAO CHEN GUI wrote: Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2021-August/578162.html Thanks On 26/8/2021 上午 9:19, HAO CHEN GUI wrote: Hi

PING^1 [PATCH, rs6000] Optimization for vec_xl_sext

Hi,   Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2021-September/579434.html Thanks On 15/9/2021 下午 3:35, HAO CHEN GUI wrote: Bill,     Yes, I built the gcc with p10 binutils. Then power10_ok tests can pass. Thanks again for your kindly explanation.     I finally realized

Re: [PATCH, rs6000] Optimization for vec_xl_sext

Bill,     Yes, I built the gcc with p10 binutils. Then power10_ok tests can pass. Thanks again for your kindly explanation.     I finally realized that the line wrap settings on my thunderbird didn't take any effect. I have to set a very large line size,  just for a workaround. ChangeLog

Re: [PATCH, rs6000] Optimization for vec_xl_sext

Bill,   Thanks so much for your advice.   I refined the patch and passed the bootstrap and regression test. Just one thing, the test case becomes unsupported on P9 if I set "{ dg-require-effective-target power10_ok }". I just want the test case to be compiled and check its assembly. Do we

[PATCH, rs6000] optimization for vec_reve builtin [PR100868]

Hi,   The patch optimized for vec_reve builtin on rs6000. For V2DI and V2DF, it is implemented by xxswapd on all targets. For V16QI, V8HI, V4SI and V4SF, it is implemented by quadword byte reverse plus halfword/word byte reverse when p9_vector is defined.   Bootstrapped and tested on

[PATCH, rs6000] Optimization for vec_xl_sext

Hi,    The patch optimized the code generation for vec_xl_sext builtin. Now all the sign extensions are done on VSX registers directly.    Bootstrapped and tested on powerpc64le-linux with no regressions. Is this okay for trunk? Any recommendations? Thanks a lot. ChangeLog 2021-09-06

[PATCH, rs6000] optimization for long long and double vec_reve [PR100868]

Hi    The patch optimized expansion for long long or double vec_reve builtin.      Bootstrapped and tested on powerpc64le-linux with no regressions. Is this okay for trunk? Any recommendations? Thanks a lot. ChangeLog 2021-09-06 Haochen Gui gcc/     * config/rs6000/altivec.md

Re: [PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2021-August/578162.html Thanks On 26/8/2021 上午 9:19, HAO CHEN GUI wrote: Hi Bill,    Thanks for your comments. Hi Segher,    Here is the ChangeLog and patch diff. Thanks. 2021-08-25 Haochen Gui gcc/     *

Re: [PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

Hi Bill,    Thanks for your comments. Hi Segher,    Here is the ChangeLog and patch diff. Thanks. 2021-08-25 Haochen Gui gcc/     * config/rs6000/rs6000-call.c (rs6000_gimple_fold_builtin):     Modify the VSX_BUILTIN_XVMINDP, ALTIVEC_BUILTIN_VMINFP,     VSX_BUILTIN_XVMAXDP,

Re: [PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

On 25/8/2021 下午 4:17, HAO CHEN GUI via Gcc-patches wrote: Hi Kewen,   Thanks for your advice. On 25/8/2021 下午 3:50, Kewen.Lin wrote: Hi Haochen, on 2021/8/25 下午3:06, HAO CHEN GUI via Gcc-patches wrote: Hi, I refined the patch according to Bill's advice. I pasted the ChangeLog

Re: [PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

Hi Kewen,   Thanks for your advice. On 25/8/2021 下午 3:50, Kewen.Lin wrote: Hi Haochen, on 2021/8/25 下午3:06, HAO CHEN GUI via Gcc-patches wrote: Hi,     I refined the patch according to Bill's advice. I pasted the ChangeLog and diff file here. If it doesn't work, please let me know. Thanks

Re: [PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

Hi,     I refined the patch according to Bill's advice. I pasted the ChangeLog and diff file here. If it doesn't work, please let me know. Thanks. 2021-08-25 Haochen Gui gcc/     * config/rs6000/rs6000-call.c (rs6000_gimple_fold_builtin):     Modify the VSX_BUILTIN_XVMINDP,

[PATCH, rs6000] Disable gimple fold for float or double vec_minmax when fast-math is not set

Hi    The patch disables gimple fold for float or double vec_min/max builtin when fast-math is not set. Two test cases are added to verify the patch.    The attachments are the patch diff and change log file.    Bootstrapped and tested on powerpc64le-linux with no regressions. Is this okay

Re: [PATCH, rs6000] fix failure test cases caused by disabling mode promotion for pseudos [PR100952]

Segher,    Thanks for your advice. I tested it. "{ dg-final { scan-rtl-dump-times {\(compare:CC \((?:and|zero_extend):(?:DI) \((?:sub)?reg:[SD]I} 1 "combine" } }" works well. On 22/7/2021 上午 6:51, Segher Boessenkool wrote: Hi! On Tue, Jul 06, 2021 at 11:11:05AM +0800, HAO CHEN GUI wrote:

Ping [PATCH, rs6000] fix failure test cases caused by disabling mode promotion for pseudos [PR100952]

Hi,   Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2021-July/574503.html Thanks. On 6/7/2021 上午 11:11, HAO CHEN GUI wrote: Hi    The patch changed matching conditions in pr81384.c and pr56605.c. The original conditions failed to match due to mode promotion disabled.   

Ping [PATCH, rs6000] fix execution failure of parity_1.f90 on P10 [PR100952]

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2021-July/575036.html Thanks On 13/7/2021 上午 9:38, HAO CHEN GUI wrote: Hi,    I refined the patch according to Segher's advice. Is this okay for trunk? Any recommendations? Thanks a lot. On 6/7/2021 上午 11:01, HAO CHEN

Re: [PATCH, rs6000] fix execution failure of parity_1.f90 on P10 [PR100952]

Hi,    I refined the patch according to Segher's advice. Is this okay for trunk? Any recommendations? Thanks a lot. On 6/7/2021 上午 11:01, HAO CHEN GUI wrote: Hi,    The patch fixed the wrong "if" fall through in "cstore4" expand, which causes comparison pattern expanded twice on P10.   

[PATCH, rs6000] fix failure test cases caused by disabling mode promotion for pseudos [PR100952]

Hi    The patch changed matching conditions in pr81384.c and pr56605.c. The original conditions failed to match due to mode promotion disabled.    The attachments are the patch diff and change log file.    Bootstrapped and tested on powerpc64le-linux with no regressions. Is this okay for

[PATCH, rs6000] fix execution failure of parity_1.f90 on P10 [PR100952]

Hi,    The patch fixed the wrong "if" fall through in "cstore4" expand, which causes comparison pattern expanded twice on P10.    The attachments are the patch diff and change log file.     Bootstrapped and tested on powerpc64le-linux with no regressions. Is this okay for trunk? Any

Re: [PATCH 2/2, rs6000] Remove mode promotion for pseudos

Segher,    I committed two patches (r12-1201 and r12-1202) into trunk. Thanks for your review and advice. On 4/6/2021 上午 1:36, Segher Boessenkool wrote: Hi! On Thu, May 20, 2021 at 05:49:49PM +0800, HAO CHEN GUI wrote: rs6000 has instructions that can do almost everything 32 bit

Re: [PATCH 2/2, rs6000] Remove mode promotion for pseudos

Hi,   Gentle ping this:   https://gcc.gnu.org/pipermail/gcc-patches/2021-May/570854.html Thanks. On 20/5/2021 下午 5:49, HAO CHEN GUI wrote: Hi,    The patch removes mode promotion for pseudos on rs6000 target.    The attachments are the patch diff and change log file.     Bootstrapped and

Re: [PATCH, rs6000] Remove mode promotion of SSA variables

Hi, On 20/5/2021 下午 9:08, Segher Boessenkool wrote: Hi! On Thu, May 20, 2021 at 04:29:07PM +0800, HAO CHEN GUI wrote: On 19/5/2021 下午 9:20, Segher Boessenkool wrote: On Wed, May 19, 2021 at 04:36:00PM +0800, HAO CHEN GUI wrote: -/* Define this macro if it is advisable to hold scalars in

[PATCH 1/2, rs6000] Remove mode promotion for pseudos

Hi,    The patch is preparatory for the patch2 - remove mode promotion for pseudos.    The attachments are the patch diff and change log file.     Bootstrapped and tested on powerpc64le-linux and powerpc64-linux (with both m32 and m64) with no regressions. Is this okay for trunk? Any

[PATCH 2/2, rs6000] Remove mode promotion for pseudos

Hi,    The patch removes mode promotion for pseudos on rs6000 target.    The attachments are the patch diff and change log file.     Bootstrapped and tested on powerpc64le-linux and powerpc64-linux (with both m32 and m64) with no regressions. Is this okay for trunk? Any recommendations?

Re: [PATCH, rs6000] Remove mode promotion of SSA variables

On 19/5/2021 下午 9:20, Segher Boessenkool wrote: Hi! On Wed, May 19, 2021 at 04:36:00PM +0800, HAO CHEN GUI wrote: On 19/5/2021 下午 4:33, HAO CHEN GUI wrote:     This patch removes mode promotion of SSA variables on rs6000 platform. It isn't "promotion of SSA variables". At the point where

Re: [PATCH, rs6000] Remove mode promotion of SSA variables

Sorry, forgot to gcc-patches On 19/5/2021 下午 4:33, HAO CHEN GUI wrote: Hi,     This patch removes mode promotion of SSA variables on rs6000 platform.     The attachment are the patch diff and change log file.     Bootstrapped and tested on powerppc64le and powerppc64be (with m32) with no

Re: [PATCH 1/2, rs6000] Add const_anchor for rs6000 [PR33699]

David & Segher,    Thanks so much for your explanation. My patch wants to enables the constant anchor on rs6000 as TARGET_ANCHOR_CONST or targetm.anchor_const is undefined. I realized that we have addi and addis instructions. So the range of the offset could be a 32 bit constant.    I put a

Re: [PATCH 1/2, rs6000] Add const_anchor for rs6000 [PR33699]

15, 2021 at 11:11:32AM +0800, HAO CHEN GUI via Gcc-patches wrote:     This patch adds const_anchor for rs6000. The const_anchor is used in cse pass. 1) This isn't suitable for stage 4. 2) Please add a test case, which shows what it does, that it is useful. 3) Does this work on other OSes than

[PATCH 2/2] Bypass BLKmode before try_const_anchors

Hi,     This patch fixes an ICE found by enabling const_anchor for rs6000. The BLKmode constant rtx is sent to try_const_anchors which causes assertion failure in try_const_anchors.     The attachment are the patch diff and change log file.     Bootstrapped and tested on powerpc64le with no

[PATCH 1/2, rs6000] Add const_anchor for rs6000 [PR33699]

Hi,     This patch adds const_anchor for rs6000. The const_anchor is used in cse pass.     The attachment are the patch diff and change log file.     Bootstrapped and tested on powerpc64le with no regressions. Is this okay for trunk? Any  recommendations? Thanks a lot. *

Re: [PATCH, rs6000] Optimization for PowerPC 64bit constant generation [PR94395]

Alan,    Thanks for your info. Just notice your patch. I will wait for your patch being reviewed. On 3/2/2021 上午 10:32, Alan Modra wrote: On Fri, Jan 29, 2021 at 11:11:23AM +0800, HAO CHEN GUI via Gcc-patches wrote:    This patch tries to optimize PowerPC 64 bit constant generation when

[PATCH, rs6000] Optimization for PowerPC 64bit constant generation [PR94395]

Hi,    This patch tries to optimize PowerPC 64 bit constant generation when the constant can be transformed from a 32 bit or 16 bit constant by rotating, shifting and mask AND.    The attachments are the patch diff file and change log file.    Bootstrapped and tested on powerpc64le with no

Re: [PATCH] Add a new pattern in 4-insn combine

Segher,     Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2020-November/560573.html Thanks a lot. On 4/1/2021 上午 10:03, HAO CHEN GUI wrote: Segher,     Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2020-November/560573.html Thanks a lot. On 11/12/2020 上午

Re: [PATCH] Add a new pattern in 4-insn combine

Segher,     Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2020-November/560573.html Thanks a lot. On 11/12/2020 上午 10:14, HAO CHEN GUI wrote: Segher,     Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2020-November/560573.html

Re: [PATCH] Add a new pattern in 4-insn combine

Segher,     Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2020-November/560573.html On 30/11/2020 上午 11:08, HAO CHEN GUI wrote: Hi,   This patch adds a new pattern(combine 4 insns to 3 insns) in 4-insn combine. In the patch, newpat is split twice. The newpat, newi2pat and

[PATCH] Add a new pattern in 4-insn combine

Hi,   This patch adds a new pattern(combine 4 insns to 3 insns) in 4-insn combine. In the patch, newpat is split twice. The newpat, newi2pat and newi1pat replace i3, i2 and i1 respectively. The 4 to 3 combine is done at the end where all former attempts fail. In 4 insn combine pre-check, the

Re: [PATCH, rs6000] Add non-relative jump table support on Power Linux

Segher,   Thanks for your comments. I have modified the patch according to your advice and committed. On 24/11/2020 上午 6:25, Segher Boessenkool wrote: Hi! Sorry this took so long. On Thu, Oct 15, 2020 at 04:46:01PM +0800, HAO CHEN GUI wrote: On 29/9/2020 上午 6:46, Segher Boessenkool wrote:

Re: [PATCH, rs6000] Add non-relative jump table support on Power Linux

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556236.html Thanks. Gui Haochen On 6/11/2020 上午 9:02, HAO CHEN GUI wrote: Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556236.html Thanks. Gui Haochen On 15/10/2020 下午 4:46,

Re: [PATCH] Put absolute address jump table in data.rel.ro.local if targets support relocations

Hi， I just tweaked the patch according to your advice and committed it. Thanks so much for your help and advice. Haochen Gui On 13/11/2020 下午 5:27, Richard Sandiford wrote: Hi, Sorry for the slow reply. Just one minor nit: HAO CHEN GUI writes: diff --git a/gcc/varasm.c b/gcc/varasm.c

Re: [PATCH, rs6000] Add non-relative jump table support on Power Linux

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556236.html Thanks. Gui Haochen On 6/11/2020 上午 9:02, HAO CHEN GUI wrote: Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556236.html Thanks. Gui Haochen On 15/10/2020 下午 4:46,

[committed] MAINTAINERS: add myself for write after approval

2020-11-13  Haochen Gui      * MAINTAINERS (Write After Approval): add myself ---  MAINTAINERS | 1 +  1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index a0216185de9..be42e1441ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -409,6 +409,7 @@ Matthew Gretton-Dann  

[PATCH] Add a new pattern in 4-insn combine

Hi, This patch adds a new pattern in 4-insn combine. It supports the following sign_extend(op: zero_extend, zero_extend) optimization. In the patch, newpat is split twice. The first split becomes newi1pat and the second becomes newi2pat. They replace i1, i2 and i3 if all of them can be

Re: [PATCH] Put absolute address jump table in data.rel.ro.local if targets support relocations

? Thanks. On 2/10/2020 上午 1:47, Richard Sandiford wrote: Sorry for the slow review. HAO CHEN GUI via Gcc-patches writes: diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 513fc5fe295..6f5bf8d7d73 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -9315,10 +9315,10

Re: [PATCH, rs6000] Add non-relative jump table support on Power Linux

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556236.html Thanks. Gui Haochen On 15/10/2020 下午 4:46, HAO CHEN GUI wrote: Segher,     I re-wrote the patch based on parameterized name.     The attachments are the patch diff file and change log file.    

Re: [PATCH] Put absolute address jump table in data.rel.ro.local if targets support relocations

I had a wrong email setting and got your reply later. I modified the patch according to your advice. Could you please review it again? Thanks. On 2/10/2020 上午 1:47, Richard Sandiford wrote: Sorry for the slow review. HAO CHEN GUI via Gcc-patches writes: diff --git a/gcc/config/mips/mips.c b

Re: [PATCH, rs6000] Add non-relative jump table support on Power Linux

Segher,     I re-wrote the patch based on parameterized name.     The attachments are the patch diff file and change log file.     Bootstrapped and tested on powerpc64le-linux-gnu with no regressions.  Is this okay for trunk? Any recommendations? Thanks a lot. On 29/9/2020 上午 6:46, Segher

Re: [PATCH] Put absolute address jump table in data.rel.ro.local if targets support relocations

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2020-September/553809.html Thanks Gui Haochen On 14/9/2020 上午 11:01, HAO CHEN GUI wrote: Hi,   Jump tables are put into text or rodata section originally. On some platforms, it gains the performance benefit from absolute

Re: [PATCH, rs6000] Add non-relative jump table support on Power Linux

Segher,     Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2020-September/553486.html Thanks Gui Haochen On 9/9/2020 下午 4:55, HAO CHEN GUI wrote: Hi Segher,     Thanks for your advice. I removed macros defined in linux64.h and linux.h. So they take relative jump tables

Re: Do we need to do a loop invariant motion after loop interchange ?

Bin, I just tested your patch on current trunk.  Here is my summary. 1. About some iv aren't moved out of inner loop (Lijia mentioned in his last email)   [local count: 955630226]:   # l_32 = PHI <1(12), l_54(21)>   # ivtmp_165 = PHI <_446(12), ivtmp_155(21)>   _26 = (integer(kind=8)) l_32;  

[PATCH] Put absolute address jump table in data.rel.ro.local if targets support relocations

Hi,   Jump tables are put into text or rodata section originally. On some platforms, it gains the performance benefit from absolute address jump tables. So I want to let absolute address jump table be relocatable.  This patch puts absolute jump table in read only relocation section if the

Re: [PATCH, rs6000] Add non-relative jump table support on Power Linux

Hi Segher,     Thanks for your advice. I removed macros defined in linux64.h and linux.h. So they take relative jump tables by default. When no-relative-jumptables is set, the absolute jump tables are taken. All things relevant to section relocations are put in another patch. Thanks again.

Do we need to do a loop invariant motion after loop interchange ?

Hi, I want to follow Lijia's work as I gained the performance benefit on some SPEC workloads by adding a im pass after loop interchange.  Could you send me the latest patches? I could do further testing. Thanks a lot. https://gcc.gnu.org/pipermail/gcc/2020-February/232091.html

Re: [PATCH] Add support for putting jump table into relocation read-only section

Hi, I revised the patch according to the advice. The attachment is the revised change log and diff file. Thanks a lot. Now it first judges if it's absolute jump table or not. Then decide if the relocation is needed.   abs_jump_table = (!CASE_VECTOR_PC_RELATIVE                           

Re: [PATCH, rs6000] Add non-relative jump table support on Power Linux

Hi, I revised the patch according to the advice. The attachment is the change log and diff file. Thanks a lot. On 20/8/2020 上午 8:14, Segher Boessenkool wrote: Hi! Sorry this took so long to review. "I lost track of this patch", what can I say :-/ On Fri, Aug 14, 2020 at 03:31:05PM +0800,

How to decide if a target supports relocations or not?

Hi, Some questions about relocation. Could anyone kindly help on them? Thanks a lot. 1 If targetm.asm_out.reloc_rw_mask () returns 0, does it mean the target doesn't support relocations in read only section. So it should be put in read-write section? 2 Here, does the read only section

Re: [PATCH] Add support for putting jump table into relocation read-only section

Segher, Please ignore the attachments in my last email. My editor cached the old things. Now they should be correct. Sorry for that. On 17/8/2020 上午 10:20, HAO CHEN GUI wrote: Segher, Seems I sent the wrong diff file. Now the attachments should be correct ones. Sorry for that. For the

Re: [PATCH] Add support for putting jump table into relocation read-only section

Segher, Seems I sent the wrong diff file. Now the attachments should be correct ones. Sorry for that. For the reloc,  my understanding is the jump table needs to be relocated if it's a non-relative jump table and PIC flag is set at the same time. //stmt.c  if (CASE_VECTOR_PC_RELATIVE  

[PATCH, rs6000] Add non-relative jump table support on Power Linux

Hi, This patch adds non-relative jump table support on Power Linux. It implements ASM_OUTPUT_ADDR_VEC_ELT and adds four new expansions for non-relative jump table in rs6000.md. It also defines a rs6000 option(mrelative-jumptables). If it's set to false, the non-relative jump table is picked

[PATCH] Add support for putting jump table into relocation read-only section

Hi, This patch adds a section selection for jump tables. The jump tables can be put into read-only data section or relocation read-only data section by the relocation flags. When the PIC flag is set and jump table is non-relative, the jump table is put into relocation read-only section.

[PATCH] Add support for putting jump table into relocation read-only section

Hi, This patch adds a section selection for jump tables. The jump tables can be put into read-only data section or relocation read-only data section by the relocation flags. When the PIC flag is set and jump table is non-relative, the jump table is put into relocation read-only section.

[PATCH, rs6000] Add non-relative jump table support for 64bit rs6000

David, Seems there is something wrong with my email box.  I lost your email. I reconfigured the box and it should be OK now. Could you inform me how to exclude AIX from the condition testing? By the ABI? Thanks a lot. Haochen Gui

[PATCH, rs6000] Add non-relative jump table support for 64bit rs6000

Hi, This patch adds non-relative jump table support for 64bit rs6000. It implements ASM_OUTPUT_ADDR_VEC_ELT and corresponding expansion of jump table instruction for 64bit rs6000. We want to put non-relative jump table in data.rel.ro section for rs6000. So I add a new target hook -

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