[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Use shNadd for constant synthesis

https://gcc.gnu.org/g:972cb5c8dbb56c378c12d2ca88b1940c1c1c1c45 commit 972cb5c8dbb56c378c12d2ca88b1940c1c1c1c45 Author: Jeff Law Date: Fri May 10 13:49:44 2024 -0600 [RISC-V] Use shNadd for constant synthesis So here's the next idiom to improve constant synthesis

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix typos in code or comment [NFC]

https://gcc.gnu.org/g:73fe7fd03bc4adeac1b5ce7619b58b60e9f5dca6 commit 73fe7fd03bc4adeac1b5ce7619b58b60e9f5dca6 Author: Kito Cheng Date: Tue May 7 10:18:58 2024 +0800 RISC-V: Fix typos in code or comment [NFC] Just found some typo when fixing bugs and then use aspell to find few

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Provide splitting guidance to combine to faciliate shNadd.uw generation

https://gcc.gnu.org/g:a4b72b2f9d6e5a560ebb42f485121d66576979ee commit a4b72b2f9d6e5a560ebb42f485121d66576979ee Author: Jeff Law Date: Thu May 9 21:07:06 2024 -0600 [committed] [RISC-V] Provide splitting guidance to combine to faciliate shNadd.uw generation This fixes a minor

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add tests for cpymemsi expansion

https://gcc.gnu.org/g:94912842c2baae5ac6a1fe0c0d91330a7376d21f commit 94912842c2baae5ac6a1fe0c0d91330a7376d21f Author: Christoph Müllner Date: Thu Apr 11 12:07:10 2024 +0200 RISC-V: Add tests for cpymemsi expansion cpymemsi expansion was available for RISC-V since the initial

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

https://gcc.gnu.org/g:6c5e2178e97baaba8ca156bc705222eae9a52f17 commit 6c5e2178e97baaba8ca156bc705222eae9a52f17 Author: Xiao Zeng Date: Wed May 8 14:00:58 2024 -0600 [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16 1 This patch implements the Nan-box of bf16.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Make full-vec-move1.c test robust for optimization

https://gcc.gnu.org/g:227ec9bfd49a7bf388f5c5ddd4f556e254c7a928 commit 227ec9bfd49a7bf388f5c5ddd4f556e254c7a928 Author: Pan Li Date: Thu May 9 10:56:46 2024 +0800 RISC-V: Make full-vec-move1.c test robust for optimization During investigate the support of early break autovec, we

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis

https://gcc.gnu.org/g:b30496ab6f0706b373ca68cea832fe13dd0c0e59 commit b30496ab6f0706b373ca68cea832fe13dd0c0e59 Author: Jeff Law Date: Wed May 8 13:44:00 2024 -0600 [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis Reposting without the patch

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add zero_extract support for rv64gc

https://gcc.gnu.org/g:76f36d93c3107544c6dbdffa616599ce3fdb44eb commit 76f36d93c3107544c6dbdffa616599ce3fdb44eb Author: Christoph Müllner Date: Mon May 6 12:33:32 2024 +0200 RISC-V: Add zero_extract support for rv64gc The combiner attempts to optimize a zero-extension of a logical

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cover sign-extensions in lshr3_zero_extend_4

https://gcc.gnu.org/g:d3660f7816fbc403a97492545a687b0651fe3429 commit d3660f7816fbc403a97492545a687b0651fe3429 Author: Christoph Müllner Date: Tue May 7 22:23:26 2024 +0200 RISC-V: Cover sign-extensions in lshr3_zero_extend_4 The lshr3_zero_extend_4 pattern targets bit extraction

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2

https://gcc.gnu.org/g:31ab40016ae2864e4aa7741a1e3b6d867a6779cc commit 31ab40016ae2864e4aa7741a1e3b6d867a6779cc Author: Christoph Müllner Date: Tue May 7 23:26:02 2024 +0200 RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2 The pattern lshrsi3_zero_extend_2 extracts the MSB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add test for sraiw-31 special case

https://gcc.gnu.org/g:929ef4d2fa08eabbf645c86ffe12ebbfb8219190 commit 929ef4d2fa08eabbf645c86ffe12ebbfb8219190 Author: Christoph Müllner Date: Tue May 7 22:59:44 2024 +0200 RISC-V: Add test for sraiw-31 special case We already optimize a sign-extension of a right-shift by 31 in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][RISC-V] Turn on overlap_op_by_pieces for generic-ooo tuning

https://gcc.gnu.org/g:30096ff9c4e5b8f31a0f65841db44f3b4fd71fda commit 30096ff9c4e5b8f31a0f65841db44f3b4fd71fda Author: Jeff Law Date: Tue May 7 15:34:16 2024 -0600 [committed][RISC-V] Turn on overlap_op_by_pieces for generic-ooo tuning Per quick email exchange with Palmer. Given

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Allow uarchs to set TARGET_OVERLAP_OP_BY_PIECES_P

https://gcc.gnu.org/g:aeadd95aeb5f6e6e0e4f1a98c93a11754f536472 commit aeadd95aeb5f6e6e0e4f1a98c93a11754f536472 Author: Christoph Müllner Date: Tue May 7 15:16:21 2024 -0600 [committed] [RISC-V] Allow uarchs to set TARGET_OVERLAP_OP_BY_PIECES_P This is almost exclusively work from

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] [PATCH v2] Enable inlining str* by default

https://gcc.gnu.org/g:411f7cc1778500ed2c5cfa26e3217b4b61a5 commit 411f7cc1778500ed2c5cfa26e3217b4b61a5 Author: Jeff Law Date: Tue May 7 11:43:09 2024 -0600 [RISC-V] [PATCH v2] Enable inlining str* by default So with Chrstoph's patches from late 2022 we've had the ability

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option

https://gcc.gnu.org/g:a38ee93f25444aea92a24e5cd9ebb948b92dcdc3 commit a38ee93f25444aea92a24e5cd9ebb948b92dcdc3 Author: Xiao Zeng Date: Mon May 6 15:57:37 2024 -0600 [PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option This patch would like to add new sub extension (aka

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcase for PR114749.

https://gcc.gnu.org/g:03d11c2142d2b375161fa50d367c2bb9bfe742bd commit 03d11c2142d2b375161fa50d367c2bb9bfe742bd Author: Robin Dapp Date: Mon May 6 15:51:37 2024 -0600 RISC-V: Add testcase for PR114749. this adds a test case for PR114749. Going to commit as obvious unless

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Add support for _Bfloat16

https://gcc.gnu.org/g:1c61e73ff62e1fc84de2bda1c35215b3d058699c commit 1c61e73ff62e1fc84de2bda1c35215b3d058699c Author: Xiao Zeng Date: Mon May 6 15:39:12 2024 -0600 [RISC-V] Add support for _Bfloat16 1 At point , BF16 has already

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Document -mcmodel=large

https://gcc.gnu.org/g:fdaac11cd9b4680ef895754de9ef09493eb2182f commit fdaac11cd9b4680ef895754de9ef09493eb2182f Author: Palmer Dabbelt Date: Mon May 6 15:34:26 2024 -0600 RISC-V: Document -mcmodel=large This slipped through the cracks. Probably also NEWS-worthy.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] So another constant synthesis improvement.

https://gcc.gnu.org/g:6c0a8dff816db539a523f9feab9d19cb2bf13f94 commit 6c0a8dff816db539a523f9feab9d19cb2bf13f94 Author: Jeff Law Date: Mon May 6 15:27:43 2024 -0600 So another constant synthesis improvement. In this patch we're looking at cases where we'd like to be able to use

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][RISC-V] Fix nearbyint failure on rv32 and formatting nits

https://gcc.gnu.org/g:733526b306158f6e68c8ef9ad7bf6adb04f4e894 commit 733526b306158f6e68c8ef9ad7bf6adb04f4e894 Author: Jeff Law Date: Thu May 2 17:13:12 2024 -0600 [committed][RISC-V] Fix nearbyint failure on rv32 and formatting nits The CI system tripped an execution failure

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: miscll comment fixes [NFC]

https://gcc.gnu.org/g:4751ac4274c4a8b21f35325aae6794c1626f16bc commit 4751ac4274c4a8b21f35325aae6794c1626f16bc Author: Vineet Gupta Date: Tue Mar 1 03:45:19 2022 -0800 RISC-V: miscll comment fixes [NFC] gcc/ChangeLog: * config/riscv/riscv.cc: Comment updates.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RFA][RISC-V] Improve constant synthesis for constants with 2 bits set

https://gcc.gnu.org/g:43130081438c423616549bf3a6b0649b84baddfc commit 43130081438c423616549bf3a6b0649b84baddfc Author: Jeff Law Date: Thu May 2 14:06:22 2024 -0600 [RFA][RISC-V] Improve constant synthesis for constants with 2 bits set In doing some preparation work for using

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Trivial pattern cleanup

https://gcc.gnu.org/g:1659526b1e18375f3a604245a0769dfa4b5548ab commit 1659526b1e18375f3a604245a0769dfa4b5548ab Author: Jeff Law Date: Wed May 1 12:43:37 2024 -0600 [committed] [RISC-V] Trivial pattern cleanup As I was reviewing and cleaning up some internal work, I noticed

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Don't run new rounding tests on newlib risc-v targets

https://gcc.gnu.org/g:d3c8cb96e4e2a04dc3765467fc609a12ca6e6e25 commit d3c8cb96e4e2a04dc3765467fc609a12ca6e6e25 Author: Jeff Law Date: Thu May 2 08:42:32 2024 -0600 [committed] [RISC-V] Don't run new rounding tests on newlib risc-v targets The new round_32.c and round_64.c tests

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Fix detection of store pair fusion cases

https://gcc.gnu.org/g:241fbf90eb65e11a028aa72e0b48529fecb3f3c9 commit 241fbf90eb65e11a028aa72e0b48529fecb3f3c9 Author: Jeff Law Date: Wed May 1 11:28:41 2024 -0600 [committed] [RISC-V] Fix detection of store pair fusion cases We've got the ability to count the number of store

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the condition for add additional vars in RVV cost model

https://gcc.gnu.org/g:0285854739ff710005770f8e956197f34fe9b967 commit 0285854739ff710005770f8e956197f34fe9b967 Author: demin.han Date: Tue Mar 26 16:52:12 2024 +0800 RISC-V: Refine the condition for add additional vars in RVV cost model The adjacent_dr_p is sufficient and

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] This is almost exclusively Jivan's work. His original post:

https://gcc.gnu.org/g:1f741dd358b094b57ca820cadf046b3fe6fbe736 commit 1f741dd358b094b57ca820cadf046b3fe6fbe736 Author: Jivan Hakobyan Date: Tue Apr 30 09:44:02 2024 -0600 This is almost exclusively Jivan's work. His original post: >

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix parsing of Zic* extensions

https://gcc.gnu.org/g:fe3b44c779a51ebf0d5c017d4c676b6cc41932ae commit fe3b44c779a51ebf0d5c017d4c676b6cc41932ae Author: Christoph Müllner Date: Mon Apr 29 00:46:06 2024 +0200 RISC-V: Fix parsing of Zic* extensions The extension parsing table entries for a range of Zic* extensions

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add -X to link spec

https://gcc.gnu.org/g:0761c4e460775424643c45a09558b8b85ad6b0a4 commit 0761c4e460775424643c45a09558b8b85ad6b0a4 Author: Fangrui Song Date: Fri Apr 26 18:14:33 2024 -0700 RISC-V: Add -X to link spec --discard-locals (-X) instructs the linker to remove local .L* symbols, which

[gcc/riscv/heads/gcc-14-with-riscv-opts] (141 commits) [to-be-committed] [RISC-V] Try inverting for constant synth

The branch 'riscv/heads/gcc-14-with-riscv-opts' was updated to point to: 7f716ba0f6c... [to-be-committed] [RISC-V] Try inverting for constant synth It previously pointed to: 19868f0990e... [to-be-committed] [RISC-V] Try inverting for constant synth Diff: !!! WARNING: THE FOLLOWING COMMITS

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant

https://gcc.gnu.org/g:f69c19f64e96e3cb04767d2f41191df114d4b309 commit f69c19f64e96e3cb04767d2f41191df114d4b309 Author: Jeff Law Date: Sun May 26 10:54:18 2024 -0600 [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant Next step

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Try inverting for constant synthesis

https://gcc.gnu.org/g:19868f0990e87159025646bf99cf461c07e12563 commit 19868f0990e87159025646bf99cf461c07e12563 Author: Jeff Law Date: Sun May 26 17:54:51 2024 -0600 [to-be-committed] [RISC-V] Try inverting for constant synthesis So there's another class of constants we're failing

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [v2] More logical op simplifications in simplify-rtx.cc

https://gcc.gnu.org/g:fee06b936580108cee30467ad5ae98be5c8d1a4f commit fee06b936580108cee30467ad5ae98be5c8d1a4f Author: Jeff Law Date: Sat May 25 12:39:05 2024 -0600 [committed] [v2] More logical op simplifications in simplify-rtx.cc This is a revamp of what started as a target

[gcc r15-838] [to-be-committed] [RISC-V] Try inverting for constant synthesis

https://gcc.gnu.org/g:3a915d6ad5fc3e0fadd14e54515b48b1d655c5a4 commit r15-838-g3a915d6ad5fc3e0fadd14e54515b48b1d655c5a4 Author: Jeff Law Date: Sun May 26 17:54:51 2024 -0600 [to-be-committed] [RISC-V] Try inverting for constant synthesis So there's another class of constants

[to-be-committed][RISC-V] Reassociate constants in logical ops

This patch from Lyut will reassociate operands when we have shifted logical operations. This can simplify a constant that may not be fit in a simm12 into a form that does fit into a simm12. The basic work was done by Lyut. I generalized it to handle XOR/OR. It stands on its own, but also

[gcc r15-835] [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant

https://gcc.gnu.org/g:95660223c434000a42957cf6cabed0236bb4bae8 commit r15-835-g95660223c434000a42957cf6cabed0236bb4bae8 Author: Jeff Law Date: Sun May 26 10:54:18 2024 -0600 [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant Next step

[to-be-committed] [RISC-V] Try inverting for constant synthesis

So there's another class of constants we're failing to synthesize well. Specifically those where we can invert our original constant C into C' and C' takes at least 2 fewer instructions to synthesize than C. In that case we can initially generate C', then use xori with the constant -1 to flip

Re: [PATCHv2 2/2] libiberty/buildargv: handle input consisting of only white space

On 2/10/24 10:26 AM, Andrew Burgess wrote: GDB makes use of the libiberty function buildargv for splitting the inferior (program being debugged) argument string in the case where the inferior is not being started under a shell. I have recently been working to improve this area of GDB, and

Re: [PATCHv2 1/2] libiberty/buildargv: POSIX behaviour for backslash handling

On 2/10/24 10:26 AM, Andrew Burgess wrote: GDB makes use of the libiberty function buildargv for splitting the inferior (program being debugged) argument string in the case where the inferior is not being started under a shell. I have recently been working to improve this area of GDB, and

Re: [PATCH] Support libcall __float{,un}sibf by SF when it is not supported for _bf16

On 12/20/23 4:17 AM, Jin Ma wrote: We don't have SI -> BF library functions, use SI -> SF -> BF instead. Although this can also be implemented in a target machine description, it is more appropriate to move into target independent code. gcc/ChangeLog: * optabs.cc (expand_float):

Re: [PATCH] gimple-vr-values:Add constraint for gimple-cond optimization

On 11/22/23 10:47 PM, Feng Wang wrote: This patch add another condition for gimple-cond optimization. Refer to the following test case. int foo1 (int data, int res) { res = data & 0xf; res |= res << 4; if (res < 0x22) return 0x22; return res; } with the compilation flag

Re: [PATCH] libcpp: Correct typo 'r' -> '\r'

On 5/25/24 11:16 AM, Peter Damianov wrote: libcpp/ChangeLog: * lex.cc (do_peek_prev): Correct typo in argument to __builtin_expect() THanks. I've pushed this to the trunk. jeff

[gcc r15-834] [PATCH] libcpp: Correct typo 'r' -> '\r'

https://gcc.gnu.org/g:87463737b9942249ceb0d0d60050adf452f44f7c commit r15-834-g87463737b9942249ceb0d0d60050adf452f44f7c Author: Peter Damianov Date: Sun May 26 08:06:14 2024 -0600 [PATCH] libcpp: Correct typo 'r' -> '\r' libcpp/ChangeLog: * lex.cc (do_peek_prev):

Re: [PATCH v1] Gen-Match: Fix gen_kids_1 right hand braces mis-alignment

On 5/25/24 6:39 PM, pan2...@intel.com wrote: From: Pan Li Notice some mis-alignment for gen_kids_1 right hand braces as below: if ((_q50 == _q20 && ! TREE_SIDE_EFFECTS (... { if ((_q51 == _q21 && ! TREE_SIDE_EFFECTS

[committed] [v2] More logical op simplifications in simplify-rtx.cc

ng to the trunk. jeff commit 05daf617ea22e1d818295ed2d037456937e23530 Author: Jeff Law Date: Sat May 25 12:39:05 2024 -0600 [committed] [v2] More logical op simplifications in simplify-rtx.cc This is a revamp of what started as a target specific patch. Basically xalan (c

[gcc r15-831] [committed] [v2] More logical op simplifications in simplify-rtx.cc

https://gcc.gnu.org/g:05daf617ea22e1d818295ed2d037456937e23530 commit r15-831-g05daf617ea22e1d818295ed2d037456937e23530 Author: Jeff Law Date: Sat May 25 12:39:05 2024 -0600 [committed] [v2] More logical op simplifications in simplify-rtx.cc This is a revamp of what started

Re: [RFC/RFA] [PATCH 04/12] RISC-V: Add CRC built-ins tests for the target ZBC.

On 5/24/24 2:41 AM, Mariam Arutunian wrote:   gcc/testsuite/gcc.target/riscv/     * crc-builtin-zbc32.c: New file.     * crc-builtin-zbc64.c: Likewise. OK once prerequisites are approved. jeff

Re: [RFC/RFA] [PATCH 12/12] Add tests for CRC detection and generation.

On 5/24/24 2:42 AM, Mariam Arutunian wrote:   gcc/testsuite/gcc.c-torture/compile/     * crc-11.c: New test.     * crc-15.c: Likewise.     * crc-16.c: Likewise.     * crc-19.c: Likewise.     * crc-2.c: Likewise.     * crc-20.c: Likewise.     * crc-24.c: Likewise.     * crc-29.c:

Re: [RFC/RFA] [PATCH 03/12] RISC-V: Add CRC expander to generate faster CRC.

On 5/24/24 2:41 AM, Mariam Arutunian wrote: If the target is ZBC or ZBKC, it uses clmul instruction for the CRC calculation. Otherwise, if the target is ZBKB, generates table-based CRC, but for reversing inputs and the output uses bswap and brev8 instructions. Add new tests to check CRC

Re: [RFC/RFA] [PATCH 02/12] Add built-ins and tests for bit-forward and bit-reversed CRCs

On 5/24/24 2:41 AM, Mariam Arutunian wrote: This patch introduces new built-in functions to GCC for computing bit- forward and bit-reversed CRCs. These builtins aim to provide efficient CRC calculation capabilities. When the target architecture supports CRC operations (as indicated by the

Re: [RFC/RFA] [PATCH 01/12] Implement internal functions for efficient CRC computation

On 5/24/24 2:41 AM, Mariam Arutunian wrote: Add two new internal functions (IFN_CRC, IFN_CRC_REV), to provide faster CRC generation. One performs bit-forward and the other bit-reversed CRC computation. If CRC optabs are supported, they are used for the CRC computation. Otherwise, table-based

Re: [RFC/RFA][PATCH 00/12] CRC optimization

On 5/24/24 2:41 AM, Mariam Arutunian wrote: Hello! This patch set detects bitwise CRC implementation loops (with branches) in the GIMPLE optimizers and replaces them with more optimal CRC implementations in RTL. These patches introduce new internal functions, built-in functions, and

Re: [PATCH v2] RISC-V: Introduce -mrvv-allow-misalign.

On 5/24/24 5:43 PM, Palmer Dabbelt wrote: I'm only reading Zicclsm as saying both scalar and vector misaligned accesses are supported, but nothing about the performance. I think it was in the vector docs.  It didn't say anything about performance, just a note that scalar & vector behavior

Re: [PATCH v2] RISC-V: Introduce -mrvv-allow-misalign.

On 5/24/24 5:39 PM, Palmer Dabbelt wrote: On Fri, 24 May 2024 16:31:48 PDT (-0700), jeffreya...@gmail.com wrote: On 5/24/24 11:14 AM, Palmer Dabbelt wrote: On Fri, 24 May 2024 09:19:09 PDT (-0700), Robin Dapp wrote: We should have something in doc/invoke too, this one is going to be

Re: [PATCH] RISC-V: Avoid splitting store dataref groups during SLP discovery

On 5/23/24 11:52 PM, Richard Biener wrote: This worked out so I pushed the change. The gcc.dg/vect/pr97428.c test is FAILing on RISC-V (it still gets 0 SLP), because of missed load permutations. I hope the followup reorg for the load side will fix this. It also FAILs

Re: [PATCH v2] RISC-V: Introduce -mrvv-allow-misalign.

On 5/24/24 11:14 AM, Palmer Dabbelt wrote: On Fri, 24 May 2024 09:19:09 PDT (-0700), Robin Dapp wrote: We should have something in doc/invoke too, this one is going to be tricky for users.  We'll also have to define how this interacts with the existing -mstrict-align. Addressed the rest in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, v2, RISC-V] Use bclri in constant synthesis

https://gcc.gnu.org/g:a08b5d4d5c6d679a9d65797eaea93aa381ece172 commit a08b5d4d5c6d679a9d65797eaea93aa381ece172 Author: Jeff Law Date: Fri May 24 07:27:00 2024 -0600 [to-be-committed,v2,RISC-V] Use bclri in constant synthesis Testing with Zbs enabled by default showed a minor

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable vectorization for vect-early-break_124-pr114403.c

https://gcc.gnu.org/g:4e981cccad14ea3add39f92378da41d203814a60 commit 4e981cccad14ea3add39f92378da41d203814a60 Author: xuli Date: Mon May 20 01:56:47 2024 + RISC-V: Enable vectorization for vect-early-break_124-pr114403.c Because "targetm.slow_unaligned_access" is set to true

Re: Question about optimizing function pointers for direct function calls

On 5/23/24 9:51 PM, Hanke Zhang via Gcc wrote: Hi, I got a question about optimizing function pointers for direct function calls in C. Consider the following scenario: one of the fields of a structure is a function pointer, and all its assignments come from the same function. Can all its

[gcc r15-821] [to-be-committed, v2, RISC-V] Use bclri in constant synthesis

https://gcc.gnu.org/g:401994d60ab38ffa9e63f368f0456eb7b08599be commit r15-821-g401994d60ab38ffa9e63f368f0456eb7b08599be Author: Jeff Law Date: Fri May 24 07:27:00 2024 -0600 [to-be-committed,v2,RISC-V] Use bclri in constant synthesis Testing with Zbs enabled by default showed

[to-be-committed][v2][RISC-V] Use bclri in constant synthesis

Testing with Zbs enabled by default showed a minor logic error. After the loop clearing things with bclri, we can only use the sequence if we were able to clear all the necessary bits. If any bits are still on, then the bclr sequence turned out to not be profitable. -- So this is

[to-be-committed] [RISC-V] Use bclri in constant synthesis

So this is conceptually similar to how we handled direct generation of bseti for constant synthesis, but this time for bclr. In the bclr case, we already have an expander for AND. So we just needed to adjust the predicate to accept another class of constant operands (those with a single bit

Re: [PATCH v2] Match: Support __builtin_add_overflow branch form for unsigned SAT_ADD

On 5/23/24 6:14 AM, Richard Biener wrote: On Thu, May 23, 2024 at 1:08 PM Li, Pan2 wrote: I have a try to convert the PHI from Part-A to Part-B, aka PHI to _2 = phi_cond ? _1 : 255. And then we can do the matching on COND_EXPR in the underlying widen-mul pass. Unfortunately, meet some

Re: RISC-V: Fix round_32.c test on RV32

On 5/22/24 12:15 PM, Palmer Dabbelt wrote: On Wed, 22 May 2024 11:01:16 PDT (-0700), jeffreya...@gmail.com wrote: On 5/22/24 6:47 AM, Jivan Hakobyan wrote: After 8367c996e55b2 commit several checks on round_32.c test started to fail. The reason is that we prevent rounding DF->SI->DF on

Re: RISC-V: Fix round_32.c test on RV32

On 5/22/24 6:47 AM, Jivan Hakobyan wrote: After 8367c996e55b2 commit several checks on round_32.c test started to fail. The reason is that we prevent rounding DF->SI->DF on RV32 and instead of a conversation sequence we get calls to appropriate library functions. gcc/testsuite/ChangeLog:  

Re: [PATCH] Fix PR rtl-optimization/115038

On 5/20/24 1:13 AM, Eric Botcazou wrote: Hi, this is a regression present on mainline and 14 branch under the form of an ICE in seh_cfa_offset from config/i386/winnt.cc on the attached C++ testcase compiled with -O2 -fno-omit-frame-pointer. The problem directly comes from the

Re: [PATCH 4/4] Testsuite updates

On 5/22/24 4:58 AM, Richard Biener wrote: RISC-V CI didn't trigger (not sure what magic is required). Both ARM and AARCH64 show that the "Vectorizing stmts using SLP" are a bit fragile because we sometimes cancel SLP becuase we want to use load/store-lanes. The RISC-V tag on the subject

Re: [PATCH] [tree-optimization/110279] fix testcase pr110279-1.c

On 5/22/24 5:46 AM, Di Zhao OS wrote: The test case is for targets that support FMA. Previously the "target" selector is missed in dg-final command. Tested on x86_64-pc-linux-gnu. Thanks Di Zhao gcc/testsuite/ChangeLog: * gcc.dg/pr110279-1.c: add target selector. Rather than list

Re: [PATCH v1 2/2] RISC-V: Add test cases for __builtin_add_overflow branchless unsigned SAT_ADD

On 5/19/24 12:37 AM, pan2...@intel.com wrote: From: Pan Li After we support branchless __builtin_add_overflow unsigned SAT_ADD from the middle end. Add more tests case to cover the functionarlities. The below test suites are passed. * The rv64gcv fully regression test.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const mat in alloca epilogue expansion

https://gcc.gnu.org/g:106d603005c774ad619103bae3b653c94b80bf9c commit 106d603005c774ad619103bae3b653c94b80bf9c Author: Vineet Gupta Date: Wed Mar 6 15:44:27 2024 -0800 RISC-V: avoid LUI based const mat in alloca epilogue expansion This is continuing on the prev patch in function

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]

https://gcc.gnu.org/g:259f9f2c67458b594fec9eac9df0ddb8a5a27867 commit 259f9f2c67458b594fec9eac9df0ddb8a5a27867 Author: Vineet Gupta Date: Mon May 13 11:46:03 2024 -0700 RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] If the constant used for stack

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Regenerate riscv.opt.urls and i386.opt.urls

https://gcc.gnu.org/g:97fb62e5969841287c275bc12b80fd950a38061b commit 97fb62e5969841287c275bc12b80fd950a38061b Author: Mark Wielaard Date: Mon May 20 13:13:02 2024 +0200 Regenerate riscv.opt.urls and i386.opt.urls risc-v added an -mfence-tso option. i386 removed Xeon Phi ISA

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] DSE: Fix ICE after allow vector type in get_stored_val

https://gcc.gnu.org/g:5ef90118a30e49ce73f48a6f3c94129374290b5c commit 5ef90118a30e49ce73f48a6f3c94129374290b5c Author: Pan Li Date: Tue Apr 30 09:42:39 2024 +0800 DSE: Fix ICE after allow vector type in get_stored_val We allowed vector type for get_stored_val when read is less

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn

https://gcc.gnu.org/g:08aaf0da2e4cb4e36df0471e532ddf1acc873e79 commit 08aaf0da2e4cb4e36df0471e532ddf1acc873e79 Author: Jeff Law Date: Sun May 19 09:56:16 2024 -0600 [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn The circumstances which

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement -m{, no}fence-tso

https://gcc.gnu.org/g:1b074bdb09654ddd7d0d10ed31133f58df0d656e commit 1b074bdb09654ddd7d0d10ed31133f58df0d656e Author: Palmer Dabbelt Date: Sat May 18 15:15:09 2024 -0600 RISC-V: Implement -m{,no}fence-tso Some processors from T-Head don't implement the `fence.tso` instruction

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve some shift-add sequences

https://gcc.gnu.org/g:03f61ba899a4e1025284ee0de2390363694190cc commit 03f61ba899a4e1025284ee0de2390363694190cc Author: Jeff Law Date: Sat May 18 15:08:07 2024 -0600 [to-be-committed,RISC-V] Improve some shift-add sequences So this is a minor fix/improvement for shift-add

Re: [PATCH v1 2/2] RISC-V: Add test cases for branch form unsigned SAT_ADD

On 5/20/24 5:01 AM, pan2...@intel.com wrote: From: Pan Li After we support branch form unsigned SAT_ADD from the middle end. Add more tests case to cover the functionarlities. The below test suites are passed. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: *

Re: [PATCH v3 2/2] RISC-V: avoid LUI based const mat in alloca epilogue expansion

On 5/20/24 5:32 PM, Vineet Gupta wrote: This is testsuite clean however there's a dwarf quirk which I want to run by the experts. The test that was tripping CI has following fragment: Before patch| After Patch --

Re: [PATCH v3 1/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]

On 5/20/24 5:32 PM, Vineet Gupta wrote: Changes since v2: - Broke out the hunk corresponding to alloca in epilogue expansion in a seperate patch. --- If the constant used for stack offset can be expressed as sum of two S12 values, the constant need not be materialized (in a reg) and

Re: [PATCH v1 2/2] RISC-V: Add test cases for __builtin_add_overflow branch form unsigned SAT_ADD

On 5/21/24 4:53 AM, pan2...@intel.com wrote: From: Pan Li After we support __builtin_add_overflow branch form unsigned SAT_ADD from the middle end. Add more tests case to cover the functionarlities. The below test suites are passed. * The rv64gcv fully regression test.

Re: [committed] PATCH for Re: Stepping down as maintainer for ARC and Epiphany

On 5/21/24 8:02 AM, Paul Koning wrote: On May 21, 2024, at 9:57 AM, Jeff Law wrote: On 5/21/24 12:05 AM, Richard Biener via Gcc wrote: On Mon, May 20, 2024 at 4:45 PM Gerald Pfeifer wrote: On Wed, 5 Jul 2023, Joern Rennecke wrote: I haven't worked with these targets in years

Re: [committed] PATCH for Re: Stepping down as maintainer for ARC and Epiphany

On 5/21/24 8:02 AM, Paul Koning wrote: On May 21, 2024, at 9:57 AM, Jeff Law wrote: On 5/21/24 12:05 AM, Richard Biener via Gcc wrote: On Mon, May 20, 2024 at 4:45 PM Gerald Pfeifer wrote: On Wed, 5 Jul 2023, Joern Rennecke wrote: I haven't worked with these targets in years

Re: [committed] PATCH for Re: Stepping down as maintainer for ARC and Epiphany

On 5/21/24 12:05 AM, Richard Biener via Gcc wrote: On Mon, May 20, 2024 at 4:45 PM Gerald Pfeifer wrote: On Wed, 5 Jul 2023, Joern Rennecke wrote: I haven't worked with these targets in years and can't really do sensible maintenance or reviews of patches for them. I am currently working

Re: [committed] PATCH for Re: Stepping down as maintainer for ARC and Epiphany

On 5/21/24 12:05 AM, Richard Biener via Gcc wrote: On Mon, May 20, 2024 at 4:45 PM Gerald Pfeifer wrote: On Wed, 5 Jul 2023, Joern Rennecke wrote: I haven't worked with these targets in years and can't really do sensible maintenance or reviews of patches for them. I am currently working

Re: [PATCH v3 2/2] RISC-V: avoid LUI based const mat in alloca epilogue expansion

On 5/20/24 5:32 PM, Vineet Gupta wrote: This is testsuite clean however there's a dwarf quirk which I want to run by the experts. The test that was tripping CI has following fragment: Before patch| After Patch --

Re: [to-be-committed][RISC-V] Eliminate redundant bitmanip operation

On 5/19/24 1:59 PM, Andrew Pinski wrote: On Sun, May 19, 2024 at 10:58 AM Jeff Law wrote: perl has some internal bitmap code. One of its implementation properties is that if you ask it to set a bit, the bit is first cleared. Unfortunately this is fairly hard to see in gimple/match due

[to-be-committed][RISC-V] Eliminate redundant bitmanip operation

perl has some internal bitmap code. One of its implementation properties is that if you ask it to set a bit, the bit is first cleared. Unfortunately this is fairly hard to see in gimple/match due to type changes in the IL. But it is easy to see in the code we get from combine. So we just

Re: [PATCH v4] DSE: Fix ICE after allow vector type in get_stored_val

On 5/2/24 7:51 PM, pan2...@intel.com wrote: From: Pan Li We allowed vector type for get_stored_val when read is less than or equal to store in previous. Unfortunately, the valididate_subreg treats the vector type's size is less than vector register as invalid. Then we will have ICE here.

[gcc r15-652] [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn

https://gcc.gnu.org/g:e1ce9c37ed68136a99d44c8301990c184ba41849 commit r15-652-ge1ce9c37ed68136a99d44c8301990c184ba41849 Author: Jeff Law Date: Sun May 19 09:56:16 2024 -0600 [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn The circumstances

Re: [PATCH] Add widening expansion of MULT_HIGHPART_EXPR for integral modes

On 5/19/24 3:40 AM, Eric Botcazou wrote: Hi, Just notice that this patch may result in some ICE when build libc++ for the riscv port, details as below. Please note not all configuration can reproduce this issue, feel free to ping me if you cannot reproduce this issue. CC more riscv port

[to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn

Repost, this time with the RISC-V tag so it's picked up by the CI system. This fixes a minor bug that showed up in the CI system, presumably with fuzz testing. Under the right circumstances, we could end trying to emit a shift-add style sequence where the to-be-shifted operand was not a

[to-be-committed][PR target/115142] Do not create invalidate shift-add insn

This fixes a minor bug that showed up in the CI system, presumably with fuzz testing. Under the right circumstances, we could end trying to emit a shift-add style sequence where the to-be-shifted operand was not a register. This naturally leads to an unrecognized insn. The circumstances

[gcc r15-647] RISC-V: Implement -m{,no}fence-tso

https://gcc.gnu.org/g:a6114c2a691112f9cf5b072c21685d2e43c76d81 commit r15-647-ga6114c2a691112f9cf5b072c21685d2e43c76d81 Author: Palmer Dabbelt Date: Sat May 18 15:15:09 2024 -0600 RISC-V: Implement -m{,no}fence-tso Some processors from T-Head don't implement the `fence.tso`

[gcc r13-8777] [committed] Fix RISC-V missing stack tie

https://gcc.gnu.org/g:162c441c9462d073c53dde87258898795bf28a5c commit r13-8777-g162c441c9462d073c53dde87258898795bf28a5c Author: Jeff Law Date: Thu Mar 21 20:41:59 2024 -0600 [committed] Fix RISC-V missing stack tie As some of you know, Raphael has been working on stack-clash

[gcc r15-646] [to-be-committed, RISC-V] Improve some shift-add sequences

https://gcc.gnu.org/g:3c9c52a1c0fa7af22f769a2116b28a0b7ea18129 commit r15-646-g3c9c52a1c0fa7af22f769a2116b28a0b7ea18129 Author: Jeff Law Date: Sat May 18 15:08:07 2024 -0600 [to-be-committed,RISC-V] Improve some shift-add sequences So this is a minor fix/improvement for shift-add

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix "Nan-box the result of movbf on soft-bf16"

https://gcc.gnu.org/g:a5445260bd42d74aabe6c11d6207d113aafe2c8c commit a5445260bd42d74aabe6c11d6207d113aafe2c8c Author: Xiao Zeng Date: Wed May 15 16:23:16 2024 +0800 RISC-V: Fix "Nan-box the result of movbf on soft-bf16" 1 According to unpriv-isa spec:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Modify _Bfloat16 to __bf16

https://gcc.gnu.org/g:af9118f721e8d586049ff4a60ff7bc5507478344 commit af9118f721e8d586049ff4a60ff7bc5507478344 Author: Xiao Zeng Date: Fri May 17 13:48:21 2024 +0800 RISC-V: Modify _Bfloat16 to __bf16 According to the description in:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add initial cost handling for segment loads/stores.

https://gcc.gnu.org/g:d6cb9a0d984a6c9ea0b548178a5cf79629be073b commit d6cb9a0d984a6c9ea0b548178a5cf79629be073b Author: Robin Dapp Date: Mon Feb 26 13:09:15 2024 +0100 RISC-V: Add initial cost handling for segment loads/stores. This patch makes segment loads and stores more

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement IFN SAT_ADD for both the scalar and vector

https://gcc.gnu.org/g:db2b829f4d45c6f14724148d1f8b2066290b3371 commit db2b829f4d45c6f14724148d1f8b2066290b3371 Author: Pan Li Date: Fri May 17 18:49:46 2024 +0800 RISC-V: Implement IFN SAT_ADD for both the scalar and vector The patch implement the SAT_ADD in the riscv backend as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] internal-fn: Do not force vcond_mask operands to reg.

https://gcc.gnu.org/g:17dfc9744f4995d3161eeba104bd86391005769b commit 17dfc9744f4995d3161eeba104bd86391005769b Author: Robin Dapp Date: Fri May 10 12:44:44 2024 +0200 internal-fn: Do not force vcond_mask operands to reg. In order to directly use constants this patch removes

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