On 9/6/07, David Edelsohn [EMAIL PROTECTED] wrote:
Matt Lee writes:
Matt The problem is, that though the loads can be optimized by pipelining
Matt them. The register allocator has created a dependency by using only r3
Matt and r4, instead of using the other volatiles.
GCC's
On 9/6/07, Dave Korn [EMAIL PROTECTED] wrote:
On 05 September 2007 23:47, Matt Lee wrote:
Registers r3 to r12 are volatiles. However, for the C code below,
struct foo {
int a[4];
} ;
struct foo p, q;
void func ()
{
memcpy (p, q, sizeof (struct foo));
}
I am
On 9/6/07, [EMAIL PROTECTED] [EMAIL PROTECTED] wrote:
Matt Lee writes:
Date: Thu, 06 Sep 2007 15:02:52 -0400
From: David Edelsohn [EMAIL PROTECTED]
Matt There is no point trying to minimize usage of volatile hard registers,
Matt is there? They are precisely there to be used up as much
On 9/6/07, Segher Boessenkool [EMAIL PROTECTED] wrote:
load r3, q + 0
load r4, q + 4
store r3, p + 0
store r4, p + 4
load r3, q + 4
load r4, q + 8
store r3, p + 4
store r4, p + 8
These last four lines should be
load r3, q + 8
load r4, q + 12
store r3,
Hello,
On my simple RISC architecture I am seeing suboptimal instruction
scheduling with GCC-4.1.1 caused by the way registers are getting
allocated. I am looking for suggestions on what could be wrong in my
description to cause the poor allocation.
More details --
Registers r3 to r12 are
, but with 3 units stages
issue,iu,wb. What does that mean? My understanding is that the number of
units seperated by , should be equal to latency. Am I right?
Thanks - Joey
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Matt Lee
Sent: 2007年9月1日 5:58
On 8/31/07, Adam Nemet [EMAIL PROTECTED] wrote:
Matt Lee [EMAIL PROTECTED] writes:
I am seeing poor scheduling in Dhrystone where a memcpy call is
expanded inline.
memcpy (dst, src, 16) ==
load 1, rA + 4
store 1, rB + 4
load 2, rA + 8
store 2, rB + 8
...
Are you sure
Hi,
I am working with GCC-4.1.1 on a simple 5-pipe stage simple scalar
RISC processors with the following description for loads and stores,
(define_insn_reservation integer 1
(eq_attr type branch,jump,call,arith,darith,icmp,nop)
issue,iu,wb)
(define_insn_reservation load 3
(eq_attr type
Hi,
Is it possible for me to write a backend that accepts certain
addressing modes for loads, while rejecting them for stores? I am not
sure how to do this with the GO_IF_LEGITIMATE_ADDRESS macro. I know
that this is not very sane, but the situation has arisen neverthless.
I want to allow only
