OK to embedded-4_7-branch.
Thanks,
Joey
On Thu, Jun 6, 2013 at 9:43 AM, Bin Cheng bin.ch...@arm.com wrote:
Hi,
This patch fixes failure of command arm-none-eabi-gcc -O2 -mthumb
-mtune=cortex-m4 ... on arm/embedded-4_7-branch by removing the assertion
in arm_cortex_v7m_branch_cost.
Is it
Following case attempts to set floating point control register and
execute floating point operation afterward. However, it doesn't works
as expected with -Os, as GCC hoists multiply operation beyond FP
control register setting.
As there is no register dependence between __set_FPSCR and multiply,
Ramana,
This issue also impacts ldrexh/ldrexb, as assembler doesn't accept
ldrexh r1, [r0, #0]. May it be backported to 4.7 by now?
Thanks - Joey
On Tue, Jul 24, 2012 at 8:09 PM, Ramana Radhakrishnan
ramana.radhakrish...@linaro.org wrote:
Hi ,
While testing my neon intrinsics work
On Fri, Jan 11, 2013 at 2:29 AM, Louis-Philippe Brais
lpbr...@bitwrangler.ca wrote:
Hi all,
The latest errata for Texas Instruments' Cortex-M3 family, updated
last October [1], contains a disturbing new problem triggered by
non-word-aligned writes to SRAM. This is the kind of errata that is
In following example, call to sbfoo isn't a tail call with -O2. GCC
analyzes local variable may be referenced in sbfoo. Is it a reasonable
analysis? In another word, is it a legal program that bar stores
address of local to a static variable, and then for sbfoo to access
it?
This issue cause a
On Fri, Aug 17, 2012 at 9:13 AM, Ian Lance Taylor i...@google.com wrote:
Looks fine to me.
Ian
Will backport to arm/embedded-4_7-branch. No sure if appropriate for
4.7 branch since it is not a stability problem.
- Joey
I'm sorry the conversation about this patch went to private
incidentally. Resend the key point.
On Tue, Jul 24, 2012 at 8:40 PM, Julian Brown jul...@codesourcery.com wrote:
On Mon, 23 Jul 2012 13:48:22 +0800
Ye Joey joey.ye...@gmail.com wrote:
Since v7m and v6m are very different. It is high
On Mon, Apr 2, 2012 at 10:11 PM, Vladimir Makarov vmaka...@redhat.com wrote:
On 03/31/2012 01:38 AM, Ye Joey wrote:
Yes, if you mean spilling in LRA. But IRA can assign union of general and
SSE classes to a pseudo if it is profitable.
Any chance for IRA not to do so, saying by introducing
On Wed, Mar 28, 2012 at 1:07 AM, Vladimir Makarov vmaka...@redhat.com wrote:
The following patch implements general spilling one class pseudos
into another class hard registers *instead of memory* in LRA.
Can't find the patch itself
- Joey
Ping^2
On Mon, Jan 16, 2012 at 11:21 AM, Ye Joey joey.ye...@gmail.com wrote:
Ping
On Tue, Dec 27, 2011 at 10:19 AM, Ye Joey joey.ye...@gmail.com wrote:
Fix PR51200. Backport trunk 182545, 182649, 182685 to 4.6.
OK to 4.6?
- Joey
2011-12-20 Bernd Schmidt ber...@codesourcery.com
Ping
On Tue, Dec 27, 2011 at 10:19 AM, Ye Joey joey.ye...@gmail.com wrote:
Fix PR51200. Backport trunk 182545, 182649, 182685 to 4.6.
OK to 4.6?
- Joey
2011-12-20 Bernd Schmidt ber...@codesourcery.com
PR middle-end/51200
* expr.c (store_field): Avoid a direct
(sh_option_override): Likewise.
2011-12-22 Joey Ye joey...@arm.com
* toplev.c (process_options): Fix typo.
testsute
2011-12-20 Bernd Schmidt ber...@codesourcery.com
PR middle-end/51200
* gcc.target/arm/volatile-bitfields-4.c: New test.
* c-c++-common
Committed to arm/embedded-4_6-branch.
2011-12-26 Joey Ye joey...@arm.com
Revert original fix and backport r182545, 182649 from mainline
Revert:
2011-11-18 Joey Ye joey...@arm.com
Port Bernd's fix to volatile bitfields
2010-12-02 Bernd Schmidt
On Thu, Dec 22, 2011 at 12:43 AM, Ian Lance Taylor i...@google.com wrote:
Terry Guo flame...@gmail.com writes:
I plan to set up daily regression test on trunk for target
ARM-NONE-EABI and post results to gcc-testresults mailing list. Which
Binutils should I use, the Binutils trunk or the
Committed.
2011-12-22 Joey Ye joey...@arm.com
* toplev.c (process_options): Fix typo.
Index: gcc/toplev.c
===
--- gcc/toplev.c(revision 182646)
+++ gcc/toplev.c(working copy)
@@ -1332,7 +1332,7
This has been fixed by Bernd's recent commit. Add a target independent
test case to track regression.
OK to trunk and 4.6?
Joey Ye joey...@arm.com
* gcc.dg/volatile-bitfields-2.c: New test.
--- gcc/testsuite/gcc.dg/volatile-bitfields-2.c (revision 0)
+++ gcc/testsuite/gcc.dg
Writing to rbp will damage stack frame. Though it is a compile only
case, better not to write rbp.
OK to s/rbp/r13 when commit it?
- Joey
On Thu, Dec 22, 2011 at 9:59 AM, Bin Cheng bin.ch...@arm.com wrote:
Hi,
This patch fixes the bug PR43491, which exists at least on
target independent test case
Joey Ye joey...@arm.com
* gcc.dg/volatile-bitfields-2.c: New test.
--- gcc/testsuite/gcc.dg/volatile-bitfields-2.c (revision 0)
+++ gcc/testsuite/gcc.dg/volatile-bitfields-2.c (revision 0)
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options -fstrict
/testsuite/
* gcc.target/arm/volatile-bitfields-4.c: New test.
* c-c++-common/abi-bf.c: New test.
Joey Ye joey...@arm.com
* gcc.dg/volatile-bitfields-2.c: New test.
* g++.dg/abi/bitfield12.C: no-strict-volatile-bitfields.
Index: gcc/toplev.c
On Wed, Nov 30, 2011 at 7:53 AM, Han Shen(沈涵) shen...@google.com wrote:
Hi, I propose to add to gcc a new option regarding stack protector -
-fstack-protector-strong, in addition to current gcc's
-fstack-protector-all, which protects ALL functions, and
-fstack-protector, which protects
Ping
On Thu, Nov 10, 2011 at 11:57 AM, Joey Ye joey...@arm.com wrote:
Trunk gcc mis-handles following volatile bitfield case on ARM target:
$ cat a.c
extern void check(int);
typedef struct {
volatile unsigned short a:8, b:8;
} BitStruct;
BitStruct bits = {1, 2};
int main ()
{
check
To raise awareness, a track at http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51200
- Joey
From tree dump we can see that there are two assignments from x, one
to unsigned and one to signed. I guess that's the reason. Apparently
there is room to improve though.
int prephitmp.8;
int * D.2027;
unsigned int D.2026;
unsigned int x.1;
int x.0;
# BLOCK 2 freq:1
# PRED:
Backport mainline r179330 to ARM/embedded-4_6-branch
Committed.
2011-09-29 Joey Ye joey...@arm.com
Backport r179330 from mainline
2011-09-29 Jiangning Liu jiangning@arm.com
* gcc/testsuite/gcc.dg/tree-ssa/predcom-1.c: Explicitly turn on
loop unroll
On Mon, Sep 5, 2011 at 1:45 AM, Thomas Klein th.r.kl...@web.de wrote:
+static int
+stack_check_work_registers (rtx *workreg)
+{
+ int reg, i, k, n, nregs;
+
+ if (crtl-args.info.pcs_variant = ARM_PCS_AAPCS_LOCAL)
+{
+ nregs = crtl-args.info.aapcs_next_ncrn;
+}
+ else
+
Ping ^ 2
On Fri, Aug 5, 2011 at 8:56 AM, Ye Joey joey.ye...@gmail.com wrote:
Ping
On Wed, Aug 3, 2011 at 8:44 AM, Joey Ye joey...@arm.com wrote:
This patch fixes PR49437 with a single line change in ARM backend
and a regression test case for ARM target
ChangeLog:
2011-08-02 Matthew
Remove Xuepeng Guo and Joey Ye from owners of branches that we're no
longer maintaining.
Index: svn.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/svn.html,v
retrieving revision 1.163
diff -u -p -r1.163 svn.html
--- svn.html8 Aug
On Fri, Jun 24, 2011 at 11:51 PM, Thomas Klein th.r.kl...@web.de wrote:
Hi
This is a ping of (http://gcc.gnu.org/ml/gcc-patches/2011-03/msg01226.html).
Repeating my request.
I would like to have a stack check for threads with small amount of stack
space per thread.
(I'm using a ARM
This is about http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38736 and I'd rather
discuss it in gcc mail list. Basicly the problem is shown as following example:
Case 1 (on x86 or x86_64):
$ cat i.h
struct s
{
char dummy0;
// align at maxmiun aligned boundary supported by this target.
From: Ian Lance Taylor [mailto:i...@google.com]:
Therefore, I propose that we do the following:
1) Introduce __attribute__ ((aligned (scalar))). This will be
documented as having a fixed value for each ABI. The value will be
guaranteed to be sufficient to hold any ordinary non-vector
Maxim and Vladimir Wrote:
Anyone can help me through this please?
It was supposed to have two latency definitions at most (one in
define_insn_reservation and another one in define_bypass). That time it
seemed enough for all processors supported by GCC. It also simplified
semantics
Vladimir Makarov [mailto:vmaka...@redhat.com] wrote:
It was supposed to have two latency definitions at most (one in
define_insn_reservation and another one in define_bypass). That time it
seemed enough for all processors supported by GCC. It also simplified
semantics definition when two
Maxim Kuvyrkov [mailto:ma...@codesourcery.com] wrote:
Yes, it does depend on this assumption and the comment states exactly that.
What I concerned is that the assumption may be broken someday, unless scheduler
guarantees it.
Which check[s] do you have in mind, the gcc_assert's? Also, out of
Maxim and Vladimir Wrote:
Anyone can help me through this please?
It was supposed to have two latency definitions at most (one in
define_insn_reservation and another one in define_bypass). That time it
seemed enough for all processors supported by GCC. It also simplified
semantics
Maybe comments at the insn pattern who emit rep\; ret can explain it:
;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
;; instruction Athlon and K8 have.
Thanks - Joey
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Etienne
袁立威 wrote:
Hi, I'm a guy working with gcc4.1.1 on itanium2. In my work, some
instrumentations are added by gcc. After instrumentation, all
specint2000 benchmarks except gzip can successfully run with
optimization flag -O3. There are some information list below:
No answer from me but hopefully
, 2008 10:00 PM
To: H.J. Lu
Cc: Ye, Joey; gcc@gcc.gnu.org; Guo, Xuepeng
Subject: Re: CFA expression failure
On Tue, Jun 24, 2008 at 08:40:18PM -0700, H.J. Lu wrote:
I think the problem is in uw_update_context_1. REG_SAVED_EXP
and REG_SAVED_VAL_EXP may use other registers as shown above
Daniel,
We generate following DWARF2 instructions for stack alignment prologue.
Basically we use expression to calculate CFA. But it run into some
segfault in libmudflap and libjava. Do you have any hints what's wrong?
DW_CFA_def_cfa: r4 (esp) ofs 4
DW_CFA_offset: r8 (eip) at cfa-4
I got following error after changing some GCC code, can anyone give me
some hints what's wrong here?
---
error: insn does not satisfy its constraints:
(insn:HI 690 689 1267 79 libgcc/config/libbid/bid_binarydecimal.c:146450
(parallel [
(set (mem/c:DI (plus:SI (reg:SI 2 cx [59])
Hi,
From i386.md, alternative 1 of *fop_sf_comm_mixed is duplicated with
*fop_sf_comm_sse. Why do we define a _mixed pattern here?
(define_insn *fop_sf_comm_mixed
[(set (match_operand:SF 0 register_operand =f,x)
(match_operator:SF 3 binary_fp_operator
Ross, Christian,
Here are the patches to implement the idea we discussed before. Can you
take a look at it or try it?
http://gcc.gnu.org/ml/gcc-patches/2008-03/msg01200.html
http://gcc.gnu.org/ml/gcc-patches/2008-03/msg01199.html
Thanks - Joey
Honza,
Honza said:
I am bit confused here. If I wanted a free register in prologue only,
I
would probably look at the caller saved ones. But I gues it is just
typo.
I don't see much value in making the register callee-saved especially
if
you say that virtual reg (pseudo?) is used
On Wed, 13 Feb 2008, H.J. Lu wrote:
Recent i386 use arbitrary register as GOT pointer only for leaf
function. When you call something, the GOT entry uses EBX too.
We use RBX for large PIC model. But I am with Michael here that I
don't
see reason why choice of register needs to be set in
Christian Schüler writes:
Please go forward with this idea!
The current implementation of force_align_arg_pointer has never worked for me.
This proposal should solve your problem. But to comfirm, I'd like to know the
root cause. force_align_arg_pointer should have guaranteed 16 bytes align.
Ye, Joey writes:
This proposal values correctness at first place. So when compile
can't
make sure a function is only called from functions with the same or
bigger
preferred-stack-boundary, it will conservatively align the stack. One
optimization is to set INCOMING = PREFERRED for local
Andrew,
My proposal is supposed not limited to i386/x86_64. Would do please
spend some time review it and see if it can really solve problem in PowerPC?
Your comments is welcome.
Thanks - Joey
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Andrew
Thanks for Ross and HJ's comments. Here is updated proposal:
Changes:
- value of REQUIRED_STACK_BOUNDARY of leaf function
- value of INCOMING_STACK_BOUNDARY
-- 0. MOTIVATION --
Some local variables (such as of __m128 type or marked with alignment
attribute) require stack aligned at a boundary
Ross Ridge wrote:
I'm currently using -fpreferred-stack-boundary without any trouble.
Your proposal would in fact generate code to align stack when it's not
necessary. This would change the behaviour of
-fpreferred-stack-boundary,
hurting performance and that's unacceptable to me.
This
-- 0. MOTIVATION --
Some local variables (such as of __m128 type or marked with alignment
attribute) require stack aligned at a boundary larger than the default
stack
boundary. Current GCC partially supports this with limitations. We are
proposing a new design to fully solve the problem.
-- 1.
: A proposal to align GCC stack
On Mon, Dec 17, 2007 at 11:25:35PM -0500, Ross Ridge wrote:
Ye, Joey writes:
i. STACK_BOUNDARY in bits, which is enforced by hardware, 32 for i386
and 64 for x86_64. It is the minimum stack boundary. It is fixed.
Strictly speaking by the above definition
I like option B. It will be very helpful to reduce software product development
time. Some software product just release with -O0 because they are not
confident releasing a version differ to the one they were debugging and testing
in.
Also in some systems -O0 simply doesn't work, which is too
Matt,
I just started working on pipeline description and I'm confused one thing in
your description.
For integer, your cpu have a 1-cycle latency, but with 3 units stages
issue,iu,wb. What does that mean? My understanding is that the number of
units seperated by , should be equal to latency.
4.3 trunk revision 126185 I got at x86_64:
libtool: compile: unable to infer tagged configuration
libtool: compile: specify a tag with `--tag'
make[6]: *** [kill.lo] Error 1
Anyone else got the same?
126184 passes. Looks like problems in this check:
r126185 | kargl | 2007-07-02 10:47:21 +0800
53 matches
Mail list logo
