eful for my project,
but I am not sure whether it is useful for GCC overall. Can I deliver the code?
And maybe you guys can check my code and refine it to have a better quality.
Thank you!
juzhe.zh...@rivai.ai
Thanks Jeff.
I will wait after Robin updated his MAINTAINERS (since I don't known what
information I need put in).
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-07-18 00:54
To: GCC Development
CC: juzhe.zh...@rivai.ai; Robin Dapp
Subject: Ju-Zhe Zhong and Robin Dapp as RISC-V review
oop vectorizer is trying to do the conversion from char -> short with
both same nunits.
But we don't support 'vec_unpack' stuff in RISC-V backend since I don't see the
case that vec_unpack can optimize the codegen of autovectorizatio for RVV.
To fix it, is it necessary to support 'vec_unpack' ?
Thanks.
juzhe.zh...@rivai.ai
cted" 1
> FAIL: gcc.dg/vect/wrapv-vect-reduc-dot-s8b.c scan-tree-dump-times vect
> "vect_recog_widen_mult_pattern: detected" 1
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-08-30 15:45
To: juzhe.zh...@rivai.ai
CC: gcc; Robin Dapp
Subject: Re: Question about wrapv-vec
I am wondering whether we do have some situations that
vec_pack/vec_unpack/vec_widen_xxx/dot_prod pattern can be beneficial for RVV ?
I have ever met some situation that vec_unpack can be beneficial when working
on SELECT_VL but I don't which case....
juzhe.zh...@rivai.ai
From: Robin
pick LMUL = 4
for both loop 1 and loop 2 since as I said above, I do the analysis base on
function not base
on the loop.
I am struggling whether we could have a good idea for such issue. Can we pass
through loop_vec_info
to 'preferred_simd_mode' target hook?
Thanks.
juzhe.zh...@rivai.ai
though preferred_simd_mode return LMUL = 8.
If we can do that, I think we can apply analysis and then adjust the cost
according to analysis.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-08-31 15:38
To: juzhe.zh...@rivai.ai
CC: gcc; richard.sandiford
Subject: Re: Question about dynamic ch
,v4,v8
sub a2,a2,a5
vsetvli zero,a5,e32,m4,ta,ma
vse32.v v4,0(a4)
add a0,a0,a3
add a1,a1,a3
add a4,a4,a3
bne a2,zero,.L3
Fantastic architecture of GCC Vector Cost model!
Thanks a lot.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-08-31 19:20
To: juzhe.zh...@rivai.ai
CC: gcc; richard.san
Hi, Richi.
>> I don't think that's "good" use of the API.
You mean I should use 'better_main_loop_than_p‘ ？
Yes. I plan to use it.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-08-31 19:29
To: juzhe.zh...@rivai.ai
CC: gcc; richard.sandiford
per_mode' is allocated size '8'.
But for RVV, I will need to push these following modes:
RVVM8QI, RVVM4QI, RVVM2QI, RVVM1QI, V128QI, V64QI, V32QI, V16QI, V8QI, V4QI,
V2QI
There are 11 modes.
Should I increase the number from 8 to 11?
Thanks.
juzhe.zh...@rivai.ai
From: Richard
nce I think I have support all middle-end features of rvv-next.
We are analyzing, and trying to figure out why. We must recover back the
performance on GCC-14.
juzhe.zh...@rivai.ai
From: Maxim Blinov
Date: 2023-11-08 12:31
To: Jeff Law
CC: gcc; kito.cheng; juzhe.zhong
Subject: Re: Lots of FAI
I see. Thanks Tamar.
I am willing to to investigate Arm's initial patch to see what else we need in
that patch.
Since min/max reduction with index can improve SPEC performance, I will take a
look at it in GCC-15.
Thanks a lot !
juzhe.zh...@rivai.ai
From: Tamar Christina
Date: 2024-
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