Is it possbile to hack I386 backend to make all function calls to be indirect function calling?

Hi, I meet a requirement to make all function calls to be indirect function calling ( for I386 GCC compiler). I am not familiar with frontend, so my first idea is to hack it from backend, change the asm output for call and call_value insn patterns, generate a related varible in data section,

Re: Reload problems with only one base reg for base + offset addressing mode

are offsetable, and some can't. I will follow your method to handle my port. Thanks! 2010/8/1 Denis Chertykov cherty...@gmail.com: 2010/7/31 redriver jiang jiang.redri...@gmail.com: Hi, Seems there are still some exceptions. During my testing, the compiler complains: ./os_core.c: In function

Re: Reload problems with only one base reg for base + offset addressing mode

by that there is only one register R18 in POINTER_REGS class. I have changed LEGITIMIZE_RELOAD_ADDRESS several times, but still can't work. Do I miss some macro definition? Could someone give some direction? Thanks! Jiang 2010/7/26 Ian Lance Taylor i...@google.com: redriver jiang jiang.redri

Re: Reload problems with only one base reg for base + offset addressing mode

Lance Taylor i...@google.com: redriver jiang jiang.redri...@gmail.com writes: Hi, You mean I should define insn like this: (define_insn *iorqi3_imm  [(set (mem:QI (match_operand:HI 0 register_operand       b))        (ior:QI (mem:QI (match_operand:HI 1 register_operand   b

Re: Reload problems with only one base reg for base + offset addressing mode

) (match_operand: 3 HI immediate_operand K) ] ... [( set_attr length 1 )]) b for R16,R17,R18, and f for R18, K for immediate operand with range 0-127? Thanks! 2010/7/20 Ian Lance Taylor i...@google.com: redriver jiang jiang.redri...@gmail.com writes: I am porting GCC

Re: Reload problems with only one base reg for base + offset addressing mode

) (match_operand: 3 HI immediate_operand K) ] ... [( set_attr length 1 )]) b for R16,R17,R18, and f for R18, K for immediate operand with range 0-127? Thanks! 2010/7/20 Ian Lance Taylor i...@google.com: redriver jiang jiang.redri...@gmail.com writes: I am porting

Reload problems with only one base reg for base + offset addressing mode

Hi, I am porting GCC to a 8bit architecture, and now I have problem on reload problem on addressing mode. Besides 15 general registers, it has three 16bit address registers, R16,R17,R18. R16,R17,R18 are able to be as base register in base address mode, but only R18 can be base regs for

Re: The usage of the clobber match_scratch

Thanks. And for But I can't see any reason to allocate a fixed scratch register. The ACC register here I use is not a fixed register for GCC. I make ACC register to be suitable for QImode operands only. 2010/4/27 Ian Lance Taylor i...@google.com: redriver jiang jiang.redri...@gmail.com

The usage of the clobber match_scratch

Hi. Right now I know confused by the usage of clobber match_scratch. The scene is as follows: 1.Target cpu is with only a 8 bit ACC register( but I make 16 virtual registers, for reload problems). 2.For HImode operands, I let them never to goto ACC combined with other virtual registers. 3.for

Re: About STARTING_FRAME_OFFSET definition

AM, redriver jiang wrote: Hi all, Can this STARTING_FRAME_OFFSET macro be defined to be a non-constant value ( changes with the current_function_args_size)? As the target process has FP+offset with postive offset( stack grows upward, and parameters in stack grows downward), for example

About STARTING_FRAME_OFFSET definition

Hi all, Can this STARTING_FRAME_OFFSET macro be defined to be a non-constant value ( changes with the current_function_args_size)? As the target process has FP+offset with postive offset( stack grows upward, and parameters in stack grows downward), for example, call foo( arg1, arg2, arg3,arg4),

Re: Is it possible to port GCC backend to a architecture with very limited hard registers?

to build a prototype porting. 2010/3/18 Ian Lance Taylor i...@google.com: redriver jiang jiang.redri...@gmail.com writes: Right now I attempts to port the GCC backend to a MCU with very limited hard registers: only one 8 bit ACC reg, one 16 bit base reg for addressing, one stats reg. I searched

Is it possible to port GCC backend to a architecture with very limited hard registers?

Hi all, Right now I attempts to port the GCC backend to a MCU with very limited hard registers: only one 8 bit ACC reg, one 16 bit base reg for addressing, one stats reg. I searched the GCC backend porting, and seems 68HC1X has the similar scene, but it use many ram simulated register. I wonder

About the unnamed insn defined in the machine.md

Hello, recently I am porting the GCC backend to a DSP. The GCC Internals document says that the unnamed insns are used to translate RTL insns to the assembler insns, but I find that the unnamed insn patterns can be used in combine phase to combine insns by reading the *arith_shiftsi insn

About Loop Pattern ----GCC porting

Hello: I am Jiang Hongjiang and recently I am porting the GCC backend to a DSP, and get puzzled about the decrement_and_branch_until_zero pattern.By Reading the GCC source, I find that this pattern is used in loop optimization, and it's used under the condition of defining the doloop_end