> -Original Message-
> From: Bernd Schmidt [mailto:ber...@codesourcery.com]
> Sent: 07 November 2012 11:24
> To: Paulo Matos
> Cc: gcc@gcc.gnu.org
> Subject: Re: Defining scheduling resource constraint
>
>
> You can effectively remove it by returning zero if a
On 11/07/2012 12:08 PM, Paulo Matos wrote:
>
>> -Original Message-
>> From: Bernd Schmidt [mailto:ber...@codesourcery.com]
>> Sent: 07 November 2012 10:48
>> To: Paulo Matos
>> Cc: gcc@gcc.gnu.org
>> Subject: Re: Defining scheduling resource constra
> -Original Message-
> From: Bernd Schmidt [mailto:ber...@codesourcery.com]
> Sent: 07 November 2012 10:48
> To: Paulo Matos
> Cc: gcc@gcc.gnu.org
> Subject: Re: Defining scheduling resource constraint
>
> Yes... I seem to remember the documentation is just wrong
On 11/07/2012 11:41 AM, Paulo Matos wrote:
> Yes, the reordering works fine. The problem is when I change the
> value of *n_readyp. The c6x port returns n_ready (which for me
> doesn't make sense since the max insns I can schedule in a cycle is 2
> which is my issue_rate), but doesn't change *n_re
> -Original Message-
> From: Bernd Schmidt [mailto:ber...@codesourcery.com]
> Sent: 06 November 2012 17:12
> To: Paulo Matos
> Cc: gcc@gcc.gnu.org
> Subject: Re: Defining scheduling resource constraint
>
> On 11/06/2012 05:50 PM, Paulo Matos wrote:
>
> &g
On 11/06/2012 05:50 PM, Paulo Matos wrote:
> I am following your advice and using sched.reorg to remove the
> instruction from the ready list. What I am doing is checking the
> register written in ready[n_ready - 1] (if any) and look for the
> remainder of the ready list for insns writing to the s
> -Original Message-
> From: Bernd Schmidt [mailto:ber...@codesourcery.com]
> Sent: 05 November 2012 16:52
> To: Paulo Matos
> Cc: gcc@gcc.gnu.org
> Subject: Re: Defining scheduling resource constraint
>
> Depends on why it schedules them in the same cycle. Ei
On 11/05/2012 06:11 PM, Paulo Matos wrote:
>> -Original Message-
>> From: Bernd Schmidt [mailto:ber...@codesourcery.com]
>> Sent: 05 November 2012 16:52
>> To: Paulo Matos
>> Cc: gcc@gcc.gnu.org
>> Subject: Re: Defining scheduling resource constraint
&g
> -Original Message-
> From: Bernd Schmidt [mailto:ber...@codesourcery.com]
> Sent: 05 November 2012 16:52
> To: Paulo Matos
> Cc: gcc@gcc.gnu.org
> Subject: Re: Defining scheduling resource constraint
>
> Depends on why it schedules them in the same cycle. Ei
> -Original Message-
> From: Joern Rennecke [mailto:joern.renne...@embecosm.com]
> Sent: 05 November 2012 16:32
> To: Paulo Matos
> Cc: gcc@gcc.gnu.org
> Subject: Re: Defining scheduling resource constraint
>
> > This cannot happen, but I am unsure about
On 11/05/2012 03:51 PM, Paulo Matos wrote:
> Hello,
>
> I am experience a problem in GCC4.7 scheduler whereby the scheduler is
> issuing two instructions that write with a cond_exec to the same register. It
> ends up looking like this:
> Cond_exec p1 != 0 : r2 <- r2 and 0xf8
> Cond_exec p0 != 0:
Quoting Paulo Matos :
Hello,
I am experience a problem in GCC4.7 scheduler whereby the scheduler
is issuing two instructions that write with a cond_exec to the same
register. It ends up looking like this:
Cond_exec p1 != 0 : r2 <- r2 and 0xf8
Cond_exec p0 != 0: r2 <- 0x10
This cannot ha
Hello,
I am experience a problem in GCC4.7 scheduler whereby the scheduler is issuing
two instructions that write with a cond_exec to the same register. It ends up
looking like this:
Cond_exec p1 != 0 : r2 <- r2 and 0xf8
Cond_exec p0 != 0: r2 <- 0x10
This cannot happen, but I am unsure about wh
13 matches
Mail list logo
