Re: How to make use of instruction scheduling to improve performance?

2007-07-29 Thread 吴曦
2007/7/29, 吴曦 [EMAIL PROTECTED]: 28 Jul 2007 12:16:51 -0700, Ian Lance Taylor [EMAIL PROTECTED]: 吴曦 [EMAIL PROTECTED] writes: 28 Jul 2007 09:04:01 -0700, Ian Lance Taylor [EMAIL PROTECTED]: 吴曦 [EMAIL PROTECTED] writes: there are some questions after I read the source code

Re: How to make use of instruction scheduling to improve performance?

2007-07-29 Thread Ian Lance Taylor
吴曦 [EMAIL PROTECTED] writes: Sorry, I didn't find that pass in gcc 4.1.1. This pass is added in the newest gcc? I see from your later message that you found it. allocation. It means that the prologue and epilogue instructions are ~~ As you have indicated, this pass happens after

Re: How to make use of instruction scheduling to improve performance?

2007-07-28 Thread Ramana Radhakrishnan
Hi, On 7/28/07, 吴曦 [EMAIL PROTECTED] wrote: I am working on gcc 4.1.1 and itanium2 architecture. I instrumented each ld and st instruction in final_scan_insn() by looking at the insn template (These instrumentations are used to do some security checks). These instrumentations

Re: How to make use of instruction scheduling to improve performance?

2007-07-28 Thread 吴曦
2007/7/28, Ramana Radhakrishnan [EMAIL PROTECTED]: Hi, On 7/28/07, 吴曦 [EMAIL PROTECTED] wrote: I am working on gcc 4.1.1 and itanium2 architecture. I instrumented each ld and st instruction in final_scan_insn() by looking at the insn template (These instrumentations

Re: How to make use of instruction scheduling to improve performance?

2007-07-28 Thread 吴曦
2007/7/28, 吴曦 [EMAIL PROTECTED]: 2007/7/28, Ramana Radhakrishnan [EMAIL PROTECTED]: Hi, On 7/28/07, 吴曦 [EMAIL PROTECTED] wrote: I am working on gcc 4.1.1 and itanium2 architecture. I instrumented each ld and st instruction in final_scan_insn() by looking at the

Re: How to make use of instruction scheduling to improve performance?

2007-07-28 Thread Ian Lance Taylor
吴曦 [EMAIL PROTECTED] writes: there are some questions after I read the source code today. 1st. if I add the instrumentation before 2nd scheduling; will gcc emit an insn which will be output as a ld instruction later? If this could happen, some ld instruction may not be instrumented... No,

Re: How to make use of instruction scheduling to improve performance?

2007-07-28 Thread 吴曦
28 Jul 2007 09:04:01 -0700, Ian Lance Taylor [EMAIL PROTECTED]: 吴曦 [EMAIL PROTECTED] writes: there are some questions after I read the source code today. 1st. if I add the instrumentation before 2nd scheduling; will gcc emit an insn which will be output as a ld instruction later? If this

Re: How to make use of instruction scheduling to improve performance?

2007-07-28 Thread Ian Lance Taylor
吴曦 [EMAIL PROTECTED] writes: 28 Jul 2007 09:04:01 -0700, Ian Lance Taylor [EMAIL PROTECTED]: 吴曦 [EMAIL PROTECTED] writes: there are some questions after I read the source code today. 1st. if I add the instrumentation before 2nd scheduling; will gcc emit an insn which will be output

How to make use of instruction scheduling to improve performance?

2007-07-27 Thread 吴曦
I am working on gcc 4.1.1 and itanium2 architecture. I instrumented each ld and st instruction in final_scan_insn() by looking at the insn template (These instrumentations are used to do some security checks). These instrumentations incur high performance overhead when running specint benchmarks.

Re: How to make use of instruction scheduling to improve performance?

2007-07-27 Thread Ian Lance Taylor
吴曦 [EMAIL PROTECTED] writes: I am working on gcc 4.1.1 and itanium2 architecture. I instrumented each ld and st instruction in final_scan_insn() by looking at the insn template (These instrumentations are used to do some security checks). These instrumentations incur high performance overhead

Re: How to make use of instruction scheduling to improve performance?

2007-07-27 Thread 吴曦
I am working on gcc 4.1.1 and itanium2 architecture. I instrumented each ld and st instruction in final_scan_insn() by looking at the insn template (These instrumentations are used to do some security checks). These instrumentations incur high performance overhead when running