On Mar 24, 2009, at 11:02 AM, Rodrigo Dominguez wrote:
When assembling this program, 'cc1' emits a 'shrl %ecx, %eax'
instruction.
The 'shr' instruction can only take an 8-bit register as the first
operand.
The emitted instruction should have been 'shrl %cl, %eax'.
Therefore, the
compilation
3 i386]$
H.J.
---
> Thank you,
>
> Rodrigo
>
>> -Original Message-
>> From: H.J. Lu [mailto:hjl.to...@gmail.com]
>> Sent: Tuesday, March 24, 2009 2:09 PM
>> To: Rodrigo Dominguez
>> Cc: gcc@gcc.gnu.org
>> Subject: Re: Inline Assembly Error
> "Rodrigo" == Rodrigo Dominguez writes:
Rodrigo> H.J, Thanks for replying but this doesn't answer my
Rodrigo> question. Shouldn't __asm__ generate the right code without
Rodrigo> using the %b1 trick? The reason I am asking is I have a 350
Rodrigo> line macro which I can't change.
GCC do
ssue? Something like an Intel/AMD/AT&T manual explaining this?
Thank you,
Rodrigo
> -Original Message-
> From: H.J. Lu [mailto:hjl.to...@gmail.com]
> Sent: Tuesday, March 24, 2009 2:09 PM
> To: Rodrigo Dominguez
> Cc: gcc@gcc.gnu.org
> Subject: Re: Inline Assembly
On Tue, Mar 24, 2009 at 11:02 AM, Rodrigo Dominguez wrote:
> Hi,
>
> While debugging a problem with Open64, I ran into a similar problem with
> GCC. I created the following unit test program:
>
> #include
>
> int main(void)
> {
> uint32_t a = 7;
> int8_t s = -1;
>
> __asm__ ("shr
Hi,
While debugging a problem with Open64, I ran into a similar problem with
GCC. I created the following unit test program:
#include
int main(void)
{
uint32_ta = 7;
int8_t s = -1;
__asm__ ("shrl %1, %0\n\t"
: "+r" (a)
: "c" (-s)
);
