I'm working with a machine that has a memory-increment insn. It's a
network-processor performance hack that allows no-latency accumulation
of statistical counters. The insn sends the increment and address to
the memory controller which does the add, avoiding the usual
long-latency
On Saturday 24 September 2005 23:35, Greg McGary wrote:
I'm working with a machine that has a memory-increment insn. It's a
network-processor performance hack that allows no-latency accumulation
of statistical counters. The insn sends the increment and address to
the memory controller which
Paul Brook [EMAIL PROTECTED] writes:
It should just work if you have the appropriate movsi pattern/alternative.
m68k has an memory-increment instruction (aka add :-).
Touche. I've had my head in RISC-land too long... 8^)
G
On Saturday 24 September 2005 23:52, Paul Brook wrote:
On Saturday 24 September 2005 23:35, Greg McGary wrote:
I'm working with a machine that has a memory-increment insn. It's a
network-processor performance hack that allows no-latency accumulation
of statistical counters. The insn sends
