David Daney wrote:
Richard,
There seems to be a small problem with the MIPS atomic memory operations
patch I recently committed
(http://gcc.gnu.org/ml/gcc-patches/2007-08/msg01290.html), in that on a
dual CPU machine it does not quite work.
You can look at
On Tue, Sep 18, 2007 at 05:12:48PM -0700, David Daney wrote:
There seems to be a small problem with the MIPS atomic memory operations
patch I recently committed
(http://gcc.gnu.org/ml/gcc-patches/2007-08/msg01290.html), in that on a
dual CPU machine it does not quite work.
You can look
On Wed, 19 Sep 2007, Ralf Baechle wrote:
Please make this loop closure branch a branch-likely. This is necessary
as a errata workaround for some processors.
Do we emulate them for MIPS I? We do emulate ll and sc and adding
sync is easy (as a no-op as support for R3000 SMP is unlikely to
Maciej W. Rozycki wrote:
On Wed, 19 Sep 2007, Ralf Baechle wrote:
Please make this loop closure branch a branch-likely. This is necessary
as a errata workaround for some processors.
Do we emulate them for MIPS I? We do emulate ll and sc and adding
sync is easy
Currently, I (and thus
On Wed, 19 Sep 2007, David Daney wrote:
Currently, I (and thus GCC 4.3) am assuming that Linux emulates 'll', 'sc' and
'sync', If sync is not emulated, we would need to adjust the code generation
so that it is not emitted on ISAs that don't support it.
While adding sync is trivial enough I
David Daney wrote:
Maciej W. Rozycki wrote:
On Wed, 19 Sep 2007, Ralf Baechle wrote:
Please make this loop closure branch a branch-likely. This is necessary
as a errata workaround for some processors.
Do we emulate them for MIPS I? We do emulate ll and sc and
adding sync is easy
Maciej W. Rozycki wrote:
On Wed, 19 Sep 2007, David Daney wrote:
Currently, I (and thus GCC 4.3) am assuming that Linux emulates 'll', 'sc' and
'sync', If sync is not emulated, we would need to adjust the code generation
so that it is not emitted on ISAs that don't support it.
While adding
On Wed, 19 Sep 2007, David Daney wrote:
I just checked myself. 'sync' is not emulated. We will have to make a change
so that it is not emitted on ISAs that do not support it.
The problem is if such software is run on a newer processor it may
silently break. Tough, I know... We should
David Daney wrote:
Maciej W. Rozycki wrote:
On Wed, 19 Sep 2007, David Daney wrote:
Currently, I (and thus GCC 4.3) am assuming that Linux emulates 'll',
'sc' and
'sync', If sync is not emulated, we would need to adjust the code
generation
so that it is not emitted on ISAs that don't
On Wed, Sep 19, 2007 at 07:12:33PM +0100, Thiemo Seufer wrote:
Another option is to depend on the setting of -mbranch-likely. By
default it is on only for the processors which implement it and do not
discourage it, i.e. these of the MIPS II, MIPS III and MIPS IV ISAs.
All MIPS
Richard,
There seems to be a small problem with the MIPS atomic memory operations
patch I recently committed
(http://gcc.gnu.org/ml/gcc-patches/2007-08/msg01290.html), in that on a
dual CPU machine it does not quite work.
You can look at http://gcc.gnu.org/bugzilla/show_bug.cgi?id=33479#c3
On Tue, Sep 18, 2007 at 05:12:48PM -0700, David Daney wrote:
I guess my basic question is: Should MIPS_COMPARE_AND_SWAP have a 'sync'
after
the 'sc'? I would have thought that 'sc' made the write visible to all CPUs,
but on the SB1 it appears not to be the case.
Yes, a barrier of some
12 matches
Mail list logo
