On 9/12/24 8:22 AM, Richard Sandiford wrote:
This has recently come up in the RISC-V space due to needing VXRM
assignments so that we can utilize the vaaddu add-with-averaging
instructions.Placement of VXRM mode switches looks optimal from an
LCM standpoint, but speculation can measurabl
Jeff Law writes:
> On 9/7/24 1:09 AM, Richard Biener wrote:
>>
>>
>>> Am 06.09.2024 um 17:38 schrieb Andrew Carlotti :
>>>
>>> Hi,
>>>
>>> I'm working on optimising assignments to the AArch64 Floating-point Mode
>>> Register (FPMR), as part of our FP8 enablement work. Claudio has already
>>> i
On 9/7/24 7:06 PM, Andrew Carlotti wrote:
I forgot to explain how FPMR is used.
The FPMR register contains a large number of fields that control the data
formats and saturation/scaling behaviour used in various fp8 conversion an
multiplication intrinsics. At present, I think there are 2^26
On 9/8/24 12:52 AM, Richard Biener wrote:
I suppose LCM could be enhanced to handle partial antic and if the
edges it speculates on are cold that might even be profitable on less
great implementations?
Yea, that's not a bad idea at all and suspect it would be useful outside
this mode swit
On Sat, Sep 07, 2024 at 09:09:52AM +0200, Richard Biener wrote:
>
>
> > Am 06.09.2024 um 17:38 schrieb Andrew Carlotti :
> >
> > Hi,
> >
> > I'm working on optimising assignments to the AArch64 Floating-point Mode
> > Register (FPMR), as part of our FP8 enablement work. Claudio has already
>
> Am 07.09.2024 um 17:56 schrieb Jeff Law :
>
>
>
> On 9/7/24 1:09 AM, Richard Biener wrote:
Am 06.09.2024 um 17:38 schrieb Andrew Carlotti :
>>>
>>> Hi,
>>>
>>> I'm working on optimising assignments to the AArch64 Floating-point Mode
>>> Register (FPMR), as part of our FP8 enablemen
On 9/7/24 1:09 AM, Richard Biener wrote:
Am 06.09.2024 um 17:38 schrieb Andrew Carlotti :
Hi,
I'm working on optimising assignments to the AArch64 Floating-point Mode
Register (FPMR), as part of our FP8 enablement work. Claudio has already
implemented FPMR as a hard register, with the i
> Am 06.09.2024 um 17:38 schrieb Andrew Carlotti :
>
> Hi,
>
> I'm working on optimising assignments to the AArch64 Floating-point Mode
> Register (FPMR), as part of our FP8 enablement work. Claudio has already
> implemented FPMR as a hard register, with the intention that FP8 intrinsic
> fu
Hi,
I'm working on optimising assignments to the AArch64 Floating-point Mode
Register (FPMR), as part of our FP8 enablement work. Claudio has already
implemented FPMR as a hard register, with the intention that FP8 intrinsic
functions will compile to a combination of an fpmr register set, followe
