Another algorithm for live-range shrinkage I am trying to restore
expression DAG and reorder insns in Sethi-Ulman enumeration style.
This would be done best in TER (actually, in place of TER but using the
same data structures it computes).
Paolo
initial performance results?
Thanks
-Ghassan
-Original Message-
From: Andrey Belevantsev [mailto:a...@ispras.ru]
Sent: Wednesday, April 08, 2009 9:25 AM
To: Vladimir Makarov
Cc: Steven Bosscher; Shobaki, Ghassan; gcc@gcc.gnu.org
Subject: Re: Fixing the pre-pass scheduler on x86 (Bug 38403
Shobaki, Ghassan wrote:
Thanks for everyone who has responded to this email thread!
That was quite informative for me although I am not yet familiar with
all the phases in GCC. I have worked on instruction scheduling and
register allocation in another compiler and am currently trying to
Steven Bosscher wrote:
On Wed, Apr 8, 2009 at 5:19 AM, Vladimir Makarov vmaka...@redhat.com wrote:
I've been working on register-pressure sensitive insn scheduling last two
months and I hope to submit this work for gcc4.5. I am implementing also a
mode in insn-scheduler to do only live range
Vladimir Makarov wrote:
Steven Bosscher wrote:
On Wed, Apr 8, 2009 at 5:19 AM, Vladimir Makarov vmaka...@redhat.com
wrote:
I've been working on register-pressure sensitive insn scheduling last
two
months and I hope to submit this work for gcc4.5. I am implementing
also a
mode in
Shobaki, Ghassan wrote:
Hi,
I am considering working on fixing the pre-pass scheduling problem on
x86 (Bug 38403). The pre-pass instruction scheduler currently increases
register pressure to a degree that causes the register allocator to
fail. Before I commit to this task, I would like to
On Wed, Apr 8, 2009 at 5:19 AM, Vladimir Makarov vmaka...@redhat.com wrote:
Shobaki, Ghassan wrote:
Hi,
I am considering working on fixing the pre-pass scheduling problem on
x86 (Bug 38403). The pre-pass instruction scheduler currently increases
register pressure to a degree that causes the
Shobaki, Ghassan wrote:
Hi,
I am considering working on fixing the pre-pass scheduling problem on
x86 (Bug 38403). The pre-pass instruction scheduler currently increases
register pressure to a degree that causes the register allocator to
fail. Before I commit to this task, I would like to
