RE: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3

2019-02-14 Thread Peng Fan
: Warning: unpredictable: identical transfer and status registers > --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3 > > Hi, > > On Wed, 13 Feb 2019, Peng Fan wrote: > > > So the fix should be the following, right? > > Yup. Thanks for your help. Thanks, Peng. > > > Ciao, > Michael.

RE: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3

2019-02-13 Thread Michael Matz
Hi, On Wed, 13 Feb 2019, Peng Fan wrote: > So the fix should be the following, right? Yup. Ciao, Michael.

RE: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3

2019-02-13 Thread Peng Fan
: Warning: unpredictable: identical transfer and status registers > --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3 > > On Feb 13 2019, Peng Fan wrote: > > > static inline int test_and_set_bit(int nr, volatile unsigned long > > *addr) { > > u32 ret; > >

RE: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3

2019-02-13 Thread Peng Fan
gt; Subject: Re: Warning: unpredictable: identical transfer and status registers > --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3 > > Hi, > > On Wed, 13 Feb 2019, Peng Fan wrote: > > > asm volatile ( > > "ldxr %3,

Re: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3

2019-02-13 Thread Michael Matz
Hi, On Wed, 13 Feb 2019, Peng Fan wrote: > asm volatile ( > "ldxr %3, %2\n\t" > "ands %1, %3, %4\n\t" > "b.ne 1f\n\t" > "orr%3, %3, %4\n\t" > "1:\n\t"

Re: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3

2019-02-13 Thread Andreas Schwab
On Feb 13 2019, Peng Fan wrote: > static inline int test_and_set_bit(int nr, volatile unsigned long *addr) > { > u32 ret; > u64 test, tmp; > > BITOPT_ALIGN(nr, addr); > > /* AARCH64_TODO: using Inner Shareable DMB at the moment, > * revisit when we will

RE: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3

2019-02-13 Thread Peng Fan
egroups.com; will.dea...@arm.com; Catalin Marinas > > Subject: Re: Warning: unpredictable: identical transfer and status registers > --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3 > > OneWed, Feb 13, 2019 at 07:13:21AM +, Peng Fan wrote: > > We met an issue when building a piece ja

Re: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3

2019-02-13 Thread Segher Boessenkool
OneWed, Feb 13, 2019 at 07:13:21AM +, Peng Fan wrote: > We met an issue when building a piece jailhouse hypervisor code, "stxr %w0, > %3, %2\n\t" is > compiled as "stxr w4,x5,[x4]" which triggers the warning > "Warning: unpredictable: identical transfer and status registers" This is not

Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3

2019-02-12 Thread Peng Fan
Hi, We met an issue when building a piece jailhouse hypervisor code, "stxr %w0, %3, %2\n\t" is compiled as "stxr w4,x5,[x4]" which triggers the warning "Warning: unpredictable: identical transfer and status registers" After folder the do while into asm code, it is compiled as "stxr w1, x4,