im; Eric Botcazou
Cc : gcc@gcc.gnu.org
Objet : Re: delay slot of conditionnal branch with no annuled jump strategy
On 10/11/13 05:51, BELBACHIR Selim wrote:
>
>> Does this happen systematically with the compare insn or is it isolated?
>
> I encountered this problem only once in gcc
On 10/11/13 05:51, BELBACHIR Selim wrote:
Does this happen systematically with the compare insn or is it isolated?
I encountered this problem only once in gcc testsuite
(gcc.c-torture/execute/builtins/strncat-chk.c).
I think the problem is quite rare because gcc does not put often a parallel
> I have a gcc 4.6.1 port that has the same sort of problems. I tried
> selectively porting some patches from later 4.6 releases, but they didn't
> seem to actually address the issue. I haven't looked at the trunk to see if
> there are patches that are more apropos.
I looked at the revision
> Does this happen systematically with the compare insn or is it isolated?
I encountered this problem only once in gcc testsuite
(gcc.c-torture/execute/builtins/strncat-chk.c).
I think the problem is quite rare because gcc does not put often a parallel
compare insn into the delay slot of a cond
I have a gcc 4.6.1 port that has the same sort of problems. I tried
selectively porting some patches from later 4.6 releases, but they didn't seem
to actually address the issue. I haven't looked at the trunk to see if there
are patches that are more apropos.
On Oct 10, 2013, at 12:33 PM, Jef
On 10/10/13 07:31, BELBACHIR Selim wrote:
Why GCC doesn't see, in this case, that it's not safe to fill the delay slot
with my compare insn (which is a parallel RTX which clobber one register used
in fallthrough branch) ?
Is a processor 'annuled jump strategy' mandatory to handle delay slot of
> Here is a sample of erroneous code :
>
>
> sub 0,$R5,$R1 #compare $R5 to 0 ($R1 is clobbered)
> jmpd.ifCC .L0#conditionnal delayed branch followed by 1
> delay slot sub $R0,$R4,$R0 #compare $R4 to $R0 ($R0 is clobbered)
> problem ..
Hi,
I'm porting gcc 4.5.2 on a private processor.
I encountered a problem concerning delay slots of conditionnal branch
instructions (Note : the processor has no 'annuled jump strategy')
Here is my delay slot definition :
(define_delay (eq_attr "type" "jump")
[(and (eq_attr "delaya
