[Bug rtl-optimization/103550] 2 more instructions generated by gcc than clang

2022-10-06 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103550 --- Comment #11 from Andrew Pinski --- *** Bug 107167 has been marked as a duplicate of this bug. ***

[Bug middle-end/107088] [13 Regression] cselib ICE building __trunctfxf2 on ia64

2022-10-06 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107088 --- Comment #11 from CVS Commits --- The master branch has been updated by Stefan Schulze Frielinghaus : https://gcc.gnu.org/g:5fc4d3e1837ea4850aac6460f563913f1d3fc5b8 commit r13-3105-g5fc4d3e1837ea4850aac6460f563913f1d3fc5b8 Author: Stefan

[Bug rtl-optimization/107167] It looks like GCC wastes registers on trivial computations when result can be cached

2022-10-06 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107167 Andrew Pinski changed: What|Removed |Added Resolution|--- |DUPLICATE

[Bug rtl-optimization/107167] It looks like GCC wastes registers on trivial computations when result can be cached

2022-10-06 Thread unlvsur at live dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107167 --- Comment #4 from cqwrteur --- (In reply to Andrew Pinski from comment #1) > Plus your example might be slower due to dependencies. Dependency is only an issue to a certain degree. 1st one it has things like "movl%edi, %edx; rorl

[Bug rtl-optimization/107167] It looks like GCC wastes registers on trivial computations when result can be cached

2022-10-06 Thread unlvsur at live dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107167 --- Comment #3 from cqwrteur --- (In reply to Andrew Pinski from comment #1) > This is a reassociation, scheduling issue and register allocation issue. > > Plus your example might be slower due to dependencies. > > Without a full example of

[Bug rtl-optimization/107167] It looks like GCC wastes registers on trivial computations when result can be cached

2022-10-06 Thread unlvsur at live dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107167 --- Comment #2 from cqwrteur --- (In reply to Andrew Pinski from comment #1) > This is a reassociation, scheduling issue and register allocation issue. > > Plus your example might be slower due to dependencies. > > Without a full example of

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