[Bug c/99155] redundant AND instructions generated to mask bit fields

2021-02-18 Thread dennisc at harding dot ca via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99155 --- Comment #2 from Dennis Cote --- Ah, I see. So the default does no optimization at all, not even redundant instruction elimination. Even -O1 completely inlines the function to 3 MOV instructions with constant values. So I have learned to

[Bug c/99155] New: redundant AND instructions generated to mask bit fields

2021-02-18 Thread dennisc at harding dot ca via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99155 Bug ID: 99155 Summary: redundant AND instructions generated to mask bit fields Product: gcc Version: 10.2.0 Status: UNCONFIRMED Severity: normal