[Bug c++/116595] default-initialization of vfloat32m1x4_t (RISCV V) or svfloat32x4_t (Armv9-a SVE) causes ICE

2024-09-03 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116595 --- Comment #5 from Kito Cheng --- GCC 14 with enable checking will trigger that as well, thanks for remind that detail, I forgot trunk will enable checking by default but release branch isn't

[Bug c++/116595] default-initialization of vfloat32m1x4_t (RISCV V) or svfloat32x4_t (Armv9-a SVE) causes ICE

2024-09-03 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116595 --- Comment #2 from Kito Cheng --- Hmmm, it's not well defined in the rvv intrinsic doc, but I suppose this should at least work (compile-able) without crash, also it seems works fine on GCC 14

[Bug target/116592] illegal operands th.vsetvli zero,0,e32,m8 with -O2 -O3 when compiling for risc-v xtheadvector

2024-09-03 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116592 Kito Cheng changed: What|Removed |Added CC||cmuellner at gcc dot gnu.org,

[Bug target/116278] [15] RISC-V: Miscompile at -O2 -fwrapv -fno-strict-aliasing

2024-08-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116278 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org,

[Bug target/116111] RISC-V: 'd' extension allowed with -mabi=ilp32e

2024-07-29 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116111 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #2 fro

[Bug target/115995] RISC-V: Can't generate portable RVV code for rv64gcv_zvl512b

2024-07-23 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115995 --- Comment #3 from Kito Cheng --- We have an internal qemu patch for adding an option to trigger this damm behavior by default, and plan to upstream soon...let me ask our Qemu folk if I can get the patch out first.

[Bug target/115795] RISC-V: vsetvl step causes wrong codegen after fusing info

2024-07-08 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115795 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #3 fro

[Bug target/115725] RISC-V: Use wrong AVL for rv64gcv_zfh_zvl512b

2024-07-01 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115725 --- Comment #13 from Kito Cheng --- FYI: PR for riscv-gnu-toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1501

[Bug target/115725] RISC-V: Use wrong AVL for rv64gcv_zfh_zvl512b

2024-07-01 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115725 --- Comment #12 from Kito Cheng --- Qemu has provide two option to fill up all-one to agnostic policy: rvv_ta_all_1s and rvv_ma_all_1s*, I guess we could enable that by default in riscv-gnu-toolchain to discover more potential bugs. * qemu-r

[Bug target/115725] RISC-V: Use wrong AVL for rv64gcv_zfh_zvl512b

2024-07-01 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115725 --- Comment #2 from Kito Cheng --- TU may not help for this case since we can't guarantee it's use v1 outside, I mean the argument is passed via a1 (pointer) rather than passed via v1.

[Bug tree-optimization/115073] New: RISC-V: Gimple fold not honor C[LT]Z_DEFINED_VALUE_AT_ZERO

2024-05-13 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115073 Bug ID: 115073 Summary: RISC-V: Gimple fold not honor C[LT]Z_DEFINED_VALUE_AT_ZERO Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Pr

[Bug target/114988] RISC-V: ICE in intrinsic __riscv_vfwsub_wf_f32mf2

2024-05-09 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114988 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #3 fro

[Bug target/114747] [13 only] [RISC-V RVV] Wrong SEW set for mixed-size intrinsics

2024-05-06 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114747 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/113095] [13 Regression] RISC-V: movcc no longer used for coremark crc functions with -mtune=sifive-7-series

2024-04-30 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113095 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/111234] [13] RISC-V: ICE in vsetvl pass

2024-04-29 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111234 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug c/114885] RISC-V: ICE of unrecog insn when graphite for both the c/c++ and fortran

2024-04-28 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114885 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |NEW CC|

[Bug target/114172] [13 only] RISC-V: ICE with riscv rvv VSETVL intrinsic

2024-04-24 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114172 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/111935] gcc ICE with risc-v vector intrinsics

2024-04-24 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111935 Kito Cheng changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/111234] [13] RISC-V: ICE in vsetvl pass

2024-04-24 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111234 --- Comment #4 from Kito Cheng --- Fixed on trunk, but still ICE on 13

[Bug target/114714] [RISC-V][RVV] ICE: insn does not satisfy its constraints (postreload)

2024-04-15 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114714 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org Ever confirmed

[Bug target/114130] [11 Regression] RISC-V: `__atomic_compare_exchange` does not use sign-extended value for RV64

2024-04-12 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114130 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/114639] [riscv] ICE in create_pre_exit, at mode-switching.cc:451

2024-04-08 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114639 --- Comment #4 from Kito Cheng --- Reduced case: ```c typedef long c; #pragma riscv intrinsic "vector" template struct d {}; struct e { using f = d<0>; }; struct g { using f = e::f; }; template using h = g::f; template long k(d); vbool16_

[Bug target/114639] [riscv] ICE in create_pre_exit, at mode-switching.cc:451

2024-04-08 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114639 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0

[Bug target/106530] RISCV documentation for -march= is very lacking

2024-02-16 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106530 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/109349] riscv: Add --print-supported-extensions

2024-02-16 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109349 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/113742] ICE: RTL check: expected elt 1 type 'i' or 'n', have 'e' (rtx set) in riscv_macro_fusion_pair_p, at config/riscv/riscv.cc:8416 with -O2 -finstrument-functions -mtune=sifive-p600-se

2024-02-04 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113742 --- Comment #1 from Kito Cheng --- Thanks, forward and assigned this to our (SiFive) engineer :)

[Bug rtl-optimization/113495] RISC-V: Time and memory awful consumption of SPEC2017 wrf benchmark

2024-01-19 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113495 --- Comment #23 from Kito Cheng --- > I am considering whether we should disable LICM for RISC-V by default if > vector is enabled ? That's will cause regression for other program, also may hurt those program not vectorized but benefited from

[Bug target/113240] Use wrong rule to pass fixed-length(size<=2*XLEN) vector argument

2024-01-04 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113240 --- Comment #6 from Kito Cheng --- > There needs to be a -Wabi warning for this too for the change between > versions. This bug only happened on trunk, and GCC 13 is OK, so I think it's not the case?

[Bug target/112929] [14] RISC-V vector: Variable clobbered at runtime

2023-12-12 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112929 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #20 fr

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

2023-12-05 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #8 fro

[Bug target/112478] riscv: asm clobbers not honored

2023-11-16 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112478 Kito Cheng changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/112109] Missing riscv vectorized strcmp (and other) expanders

2023-11-15 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112109 --- Comment #1 from Kito Cheng --- Just note: I would like to introduce `-mstringop-strategy=`, `-mmemcpy-strategy=` and -mmemset-strategy=` option to control the behavior like x86. the possible option list from my mind is: - auto: current st

[Bug target/112537] Is there a way to disable cpymem pass for rvv

2023-11-14 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112537 --- Comment #11 from Kito Cheng --- It's not scope of auto vectorization, so I would suggest add something like `-mstringop-strategy=*` or `-mmemcpy-strategy=*` (from x86) or `-param=riscv-mops-memcpy-size-threshold=` (from aarch64). Personally

[Bug target/112537] Is there a way to disable cpymem pass for rvv

2023-11-14 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112537 --- Comment #8 from Kito Cheng --- That remind me we may need one option like something -mgeneral-regs-only in aarch64 and also for target attribute. BTW, clang has an generic option called -mno-implicit-float can did similar thing

[Bug target/112478] riscv: asm clobbers not honored

2023-11-14 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112478 --- Comment #8 from Kito Cheng --- Proposed fix: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636466.html

[Bug target/112527] RVV integer vector instructions generated with rv64gc_zvfh

2023-11-14 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112527 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #1 fro

[Bug target/112478] riscv: asm clobbers not honored

2023-11-13 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112478 Kito Cheng changed: What|Removed |Added Ever confirmed|0 |1 CC|

[Bug target/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

2023-11-13 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433 --- Comment #4 from Kito Cheng --- Yeah, 3 major goal in LLVM is improving scheduling, partial spilling and re-materialization, but none of those points are issue for RISC-V GCC :P Ref: https://docs.google.com/presentation/d/1BOYNYKe1T-u3Q5HXRr

[Bug target/112438] RISC-V: Wrong auto-vectorization on induction variable of RVV

2023-11-08 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112438 --- Comment #12 from Kito Cheng --- oh, yeah, you are right, it already take a5 to splat, so it's right, and as you said it must be VLMAX, unless it AVL prorogation for both splat and the following vadd.vv

[Bug target/112438] RISC-V: Wrong auto-vectorization on induction variable of RVV

2023-11-08 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112438 --- Comment #10 from Kito Cheng --- (In reply to JuzheZhong from comment #9) > I have a draft patch to fix it: > > foo: > ble a0,zero,.L5 > vsetvli a5,zero,e32,m1,ta,ma > vid.v v2 > .L3: > vsetvli a5,a0,e32,m1,ta,m

[Bug target/112438] RISC-V: Wrong auto-vectorization on induction variable of RVV

2023-11-08 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112438 --- Comment #8 from Kito Cheng --- > Oh. I understand it now. I think it's a bug. > > And.. I just take a look at my internal LLVM... > Also has same issue > > I think we need to adapt the Gimple IR here: > > _35 = .SELECT_VL (ivtmp_33,

[Bug target/112438] RISC-V: Failed to AVL propagation through induction variable

2023-11-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112438 --- Comment #6 from Kito Cheng --- The key is the splat of VLMAX instruction need move into loop body, but AVL propagation should still able to do: ``` foo(int, int*, int*): ble a0,zero,.L5 csrra5,vlenb srlia

[Bug target/112438] RISC-V: Failed to AVL propagation through induction variable

2023-11-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112438 --- Comment #5 from Kito Cheng --- Assume: VLEN = 128 and n = 5, *in is {0, 0, 0, 0, 0} so VLMAX = 4 for e32m1 It can be run with vl = 4 for first iteration, and vl = 1 vl for second iteration But it could be something like that: vl = 3 for f

[Bug target/112438] RISC-V: Failed to AVL propagation through induction variable

2023-11-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112438 --- Comment #2 from Kito Cheng --- oh, but the root cause might be little bit deeper, not just the problem of propagation or not propagation the AVL.

[Bug target/112438] RISC-V: Failed to AVL propagation through induction variable

2023-11-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112438 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #1 fro

[Bug c/112431] RISC-V GCC-15 feature: Support register overlap on widen RVV instructions

2023-11-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112431 --- Comment #3 from Kito Cheng --- Share some thought from my end: we've tried at least 3 different approach on LLVM side before, and now we model that as "partial early clobber", we plan to upstream this on LLVM side but just didn't get high e

[Bug c/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

2023-11-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433 --- Comment #1 from Kito Cheng --- Give few more background why LLVM must do that way: LLVM can't allocate new pseudo register during register allocation process, however spilling vector register with specific length may require scratch register

[Bug target/112092] RISC-V: Wrong RVV code produced for vsetvl-11.c and vsetvlmax-8.c

2023-10-25 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112092 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #4 fro

[Bug target/111926] RISC-V: Use vsetvl insn replace csrr vlenb insn

2023-10-22 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111926 --- Comment #2 from Kito Cheng --- Forgot to mention, personally I love idea to simplify code gen, I could imagine that's definitely an optimization for specific uarch :)

[Bug target/111926] RISC-V: Use vsetvl insn replace csrr vlenb insn

2023-10-22 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111926 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #1 fro

[Bug tree-optimization/111791] New: RISC-V: Strange loop vectorizaion on popcount function

2023-10-12 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111791 Bug ID: 111791 Summary: RISC-V: Strange loop vectorizaion on popcount function Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal Priority: P3 C

[Bug target/111600] [14 Regression] RISC-V bootstrap time regression

2023-10-03 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111600 --- Comment #14 from Kito Cheng --- Some info for generated files: - File blankcomment code

[Bug bootstrap/111664] [14 regression] Fails to build with mawk (error in gcc/opt-read.awk) after r14-4354-ge4a4b8e983bac8

2023-10-02 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111664 Kito Cheng changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/111600] [14 Regression] RISC-V bootstrap time regression

2023-10-02 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111600 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #13 fr

[Bug target/111412] RISC-V:ICE in phase 6 of vsetvl pass

2023-09-18 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111412 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/111372] libgcc: RISCV C++ exception handling stack usage grew in 13.1

2023-09-13 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111372 --- Comment #5 from Kito Cheng --- > Ok, but it's better to have configure option or something else just > for toolchains that definitely do not use vector extension I can understand that there would be such a demand in the embedded world, but

[Bug target/110277] RISC-V: ICE when build RVV intrinsic float reduction with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13.

2023-09-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110277 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC|

[Bug target/110299] RISC-V: ICE when build RVV intrinsic widen with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13.

2023-09-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110299 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC|

[Bug target/111037] RISC-V: Invalid vsetvli fusion

2023-09-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111037 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/111074] RISC-V: segmentation fault during RTL pass: vsetvl

2023-09-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111074 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/110560] internal compiler error: in extract_constrain_insn_cached, at recog.cc:2704

2023-09-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110560 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/109773] RISC-V: ICE when build RVV Intrinsic in Both GCC 13 && GCC 14

2023-09-07 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109773 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/109725] [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430

2023-08-29 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109725 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #6 fro

[Bug target/111065] [RISCV] t-linux-multilib specifies incorrect multilib reuse patterns

2023-08-18 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111065 --- Comment #4 from Kito Cheng --- I guess I skip too much detail here, the multilib for linux isn’t really honor to the reause rule in the multilib config file for a while. That just control how multilib build, e.g. build ilp32 with which arch

[Bug target/111065] [RISCV] t-linux-multilib specifies incorrect multilib reuse patterns

2023-08-18 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111065 Kito Cheng changed: What|Removed |Added Version|og13 (devel/omp/gcc-13) |14.0 CC|

[Bug target/111037] New: RISC-V: Invalid vsetvli fusion

2023-08-16 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111037 Bug ID: 111037 Summary: RISC-V: Invalid vsetvli fusion Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/110812] Missing TARGET_OPTION_SAVE/RESTORE on riscv

2023-07-26 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110812 Kito Cheng changed: What|Removed |Added Status|NEW |ASSIGNED CC|

[Bug target/110751] RISC-V: Suport undefined value that allows VSETVL PASS use TA/MA

2023-07-20 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 --- Comment #4 from Kito Cheng --- > OK, so TA is either merge or all-ones. Yes, your understand is correct, just few more detail is that can be mixing with either merge or all-ones. e.g. An 4 x i32 vector with mask 1 0 1 0 Op = | a | b |

[Bug target/110748] RISC-V: optimize store of DF 0.0

2023-07-19 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110748 --- Comment #2 from Kito Cheng --- And seems we already has such constraint for a while, not sure why GCC 13 did that, I saw the status has changed to ASSIGNED, so I assume Vineet you are already spending time on that, so I will just stop there

[Bug target/110748] RISC-V: optimize store of DF 0.0

2023-07-19 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110748 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #1 fro

[Bug target/110696] RISC-V: -march doesn't imply correctly

2023-07-17 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110696 Kito Cheng changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/110478] RISC-V multilib gcc zicsr in the -march causing incorrect libgcc to be used

2023-06-29 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110478 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #3 fro

[Bug target/110448] [RISC-V] RVV intrinsic api test error

2023-06-29 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110448 Kito Cheng changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRMED

[Bug target/110448] [RISC-V] RVV intrinsic api test error

2023-06-28 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110448 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #1 fro

[Bug target/110264] internal compiler error: riscv_vector::vector_insn_info::get_avl_reg_rtx

2023-06-26 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110264 Kito Cheng changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/110188] gcc for RISC-V stack aligned error

2023-06-09 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110188 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #5 fro

[Bug target/109972] RISC-V: Could use umodsi3/udivsi3/divsi3 libcalls for 32-bit division/remainder on RV64 without M extension

2023-06-02 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109972 --- Comment #3 from Kito Cheng --- We care but it's lower priority compare to other configuration, so create bug to tracking here should be best solution for now :P

[Bug target/109974] RISCV: RVV VSETVL Pass ICE in SLP auto-vectorization

2023-05-29 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109974 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/109547] [13] RISC-V: Multiple vsetvli for load/store loop

2023-05-29 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109547 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/109743] RISC-V: Unnecessary VSETVLI of the RVV intrinsic in loop

2023-05-12 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109743 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/109748] RISC-V: Mis code gen for the RVV intrinsic VSETVL

2023-05-05 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109748 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/109748] RISC-V: Mis code gen for the RVV intrinsic VSETVL

2023-05-05 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109748 --- Comment #1 from Kito Cheng --- Is this also happened in GCC 13 branch?

[Bug target/109535] [13 regression] internal compiler error: in finalize_new_accesses, at rtl-ssa/changes.cc:471

2023-05-03 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109535 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/109617] RISC-V: ICE for vlmul_ext_v intrinsic API

2023-05-02 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109617 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/109272] RISCV: vbool*_t opportunities of a better code generation

2023-04-25 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109272 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/109547] [13] RISC-V: Multiple vsetvli for load/store loop

2023-04-20 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109547 Kito Cheng changed: What|Removed |Added Summary|RISC-V: Multiple vsetvli|[13] RISC-V: Multiple |f

[Bug target/109535] [13/14] internal compiler error: in finalize_new_accesses, at rtl-ssa/changes.cc:471

2023-04-20 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109535 Kito Cheng changed: What|Removed |Added Target Milestone|--- |13.2 Summary|internal compiler

[Bug target/109547] RISC-V: Multiple vsetvli for load/store loop

2023-04-18 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109547 Kito Cheng changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/109535] internal compiler error: in finalize_new_accesses, at rtl-ssa/changes.cc:471

2023-04-17 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109535 Kito Cheng changed: What|Removed |Added Last reconfirmed||2023-04-17 Status|UNCONFIRMED

[Bug target/109104] [13/14 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

2023-04-17 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104 Kito Cheng changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/109535] internal compiler error: in finalize_new_accesses, at rtl-ssa/changes.cc:471

2023-04-17 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109535 --- Comment #5 from Kito Cheng --- Confirmed the the output is text file, it's just suffixed with .out

[Bug target/109479] [RISC-V] Build vint64m1_t with rv64gc_zve32x_zvl64b should promote information like "vint64m1_t requires the 'zve64x' extensions"

2023-04-12 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109479 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/109479] [RISC-V] Build with rv64gc_zve32x_zvl64b should fail but actually not

2023-04-11 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109479 Kito Cheng changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug bootstrap/109461] build gcc for riscv target failed with `execvp: /bin/sh: Argument list too long error when using with --with-multilib-generator`

2023-04-09 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109461 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #2 fro

[Bug target/109328] [13 Regression] Build fail in RISC-V port

2023-03-31 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109328 Kito Cheng changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/109349] riscv: Add --print-supported-extensions

2023-03-30 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109349 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #4 fro

[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

2023-03-30 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104 Kito Cheng changed: What|Removed |Added Status|NEW |ASSIGNED CC|

[Bug target/109328] [13 Regression] Build fail in RISC-V port

2023-03-30 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109328 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org Status

[Bug target/109312] Missing __riscv_v_intrinsic

2023-03-28 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109312 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/109228] warning: implicit declaration of function '__riscv_vlenb'

2023-03-22 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109228 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

  1   2   >