[Bug target/121606] -march=native on AVX10.1 capable host warns about -mno-evex512

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121606 --- Comment #14 from Marko Mäkelä --- I realized that I can simply revert the changes that I had made to the compiler detection in https://github.com/dr-m/crc32_simd/ (a C++11 port of the CRC-32 assembler routines in https://github.com/intel/int

[Bug target/121606] -march=native on AVX10.1 capable host warns about -mno-evex512

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121606 --- Comment #11 from Marko Mäkelä --- I apologize for my inaccurate claim that the AMD Zen 5 would be capable of full AVX10.1. In any case, EVEX512 definitely is supported. Based on https://en.wikipedia.org/wiki/Advanced_Vector_Extensions#AVX10

[Bug c/121606] New: -march=native on AVX10.1 capable host warns about -mno-evex512

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121606 Bug ID: 121606 Summary: -march=native on AVX10.1 capable host warns about -mno-evex512 Product: gcc Version: 15.2.0 Status: UNCONFIRMED Severity: normal

[Bug middle-end/102566] [i386] GCC should emit LOCK BTS for simple bit-test-and-set operations with std::atomic

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102566 --- Comment #33 from Marko Mäkelä --- When it comes to toggling the most significant bit, std::atomic::fetch_xor() could be translated to LOCK XADD which would be able to return all bits: #include uint32_t toggle_by_add(std::atomic& a) { ret

[Bug target/107456] std::atomic::fetch_xxx generate LOCK CMPXCHG instead of simpler LOCK instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107456 --- Comment #2 from Marko Mäkelä --- Sorry for the noise. I posted a variant of the program to https://github.com/llvm/llvm-project/issues/58685 and g++-12 is already emitting the optimal code. Example: #include bool lock_add_sete(std::atomic

[Bug c++/107462] New: Missed optimization of std::atomic::fetch_xxx "null operations" to std::atomic::load()

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107462 Bug ID: 107462 Summary: Missed optimization of std::atomic::fetch_xxx "null operations" to std::atomic::load() Product: gcc Version: 12.2.0 Status: UNCONFIRMED

[Bug c++/107456] New: std::atomic::fetch_xxx generate LOCK CMPXCHG instead of simpler LOCK instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107456 Bug ID: 107456 Summary: std::atomic::fetch_xxx generate LOCK CMPXCHG instead of simpler LOCK instructions Product: gcc Version: 12.2.0 Status: UNCONFIRMED Seve

[Bug middle-end/102566] [i386] GCC should emit LOCK BTS for simple bit-test-and-set operations with std::atomic

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102566 Marko Mäkelä changed: What|Removed |Added CC||marko.makela at mariadb dot com --- Comm

[Bug sanitizer/98669] SIGSEGV on pc=0 in crypt() with -fsanitize=address

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98669 --- Comment #13 from Marko Mäkelä --- Thank you. I have reported this upstream: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=980110

[Bug sanitizer/98669] SIGSEGV on pc=0 in crypt() with -fsanitize=address

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98669 --- Comment #2 from Marko Mäkelä --- I cannot reproduce this with Debian's gcc-9 package on my system: Architecture: amd64 Version: 9.3.0-20 gcc-9 -fsanitize=address crypt.c -lcrypt && ./a.out sasWQy9ecMDEs If I change the invocation to gcc or

[Bug sanitizer/98669] New: SIGSEGV on pc=0 in crypt() with -fsanitize=address

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98669 Bug ID: 98669 Summary: SIGSEGV on pc=0 in crypt() with -fsanitize=address Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severity: normal Priority: P3 Componen