https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114923
--- Comment #9 from nfxjfg at googlemail dot com ---
Oh, I completely missed that your statement was restricted to "in HW". Normally
there are mechanisms in place that make all CPU-level memory accesses to
registers strictly ordere
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114923
--- Comment #7 from nfxjfg at googlemail dot com ---
> Note also the order of the writes to reg1 and reg2 might happen in a
> different order in HW so you need to have a full (HW) write barrier between
> them to make sure the writ
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114923
--- Comment #3 from nfxjfg at googlemail dot com ---
I'm expecting gcc to realize that the pointer escaped into the unknown, and
that it can't assume that the memory won't change. This is just causality, not
any vague made up viralyness.
Anyway
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114923
--- Comment #1 from nfxjfg at googlemail dot com ---
To make this explicitly clear: I expect that gcc reads back the buf value from
memory and returns that.
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: nfxjfg at googlemail dot com
Target Milestone: ---
Created attachment 58088
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58088=edit
Test case
In this test case, the poin
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90181
--- Comment #6 from nfxjfg at googlemail dot com ---
Yes, it's clear that that the constraint can't be _just_ the register name,
since they'll clash with builtin constraints now or with future architectures
(which may add arbitrary register names
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90181
--- Comment #3 from nfxjfg at googlemail dot com ---
Yes, it's documented this way, but it makes it appear all kinds of fragile. For
one, I normally expect that the compiler will reorder and interleave any
statements in my code (because that's
Severity: normal
Priority: P3
Component: inline-asm
Assignee: unassigned at gcc dot gnu.org
Reporter: nfxjfg at googlemail dot com
Target Milestone: ---
Currently, inline assembler constraints have no way to select an explicitly
named register
