[Bug rtl-optimization/92796] [10 Regression] ICE in lra_assign, at lra-assigns.c:1646 on powerpc64le-linux-gnu

2019-12-09 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92796 --- Comment #10 from Vladimir Makarov --- (In reply to Vladimir Makarov from comment #7) > > > I'm guessing this was never a problem before I added the code to not add > conflicts for copies. Before then, any two pseudos/registers that were li

[Bug rtl-optimization/92796] [10 Regression] ICE in lra_assign, at lra-assigns.c:1646 on powerpc64le-linux-gnu

2019-12-09 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92796 --- Comment #8 from Vladimir Makarov --- (In reply to Vladimir Makarov from comment #7) > A very interesting case, Peter. I reproduced the case too. I can take it > from here if you don't mind. The solution I see for this problem is to > chec

[Bug rtl-optimization/92796] [10 Regression] ICE in lra_assign, at lra-assigns.c:1646 on powerpc64le-linux-gnu

2019-12-09 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92796 --- Comment #7 from Vladimir Makarov --- (In reply to Peter Bergner from comment #6) > > Vlad (or Jeff), can you point me to where this is supposed to be handled? > I don't think I see where LRA verifies the reg_renumber[regno] values are > stil

[Bug rtl-optimization/92176] LRA problem with reloads for subreg operands

2019-12-06 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92176 --- Comment #9 from Vladimir Makarov --- Thank you, Andreas. I've committed the patch with your changes in the test.

[Bug rtl-optimization/92176] LRA problem with reloads for subreg operands

2019-12-06 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92176 --- Comment #8 from Vladimir Makarov --- Author: vmakarov Date: Fri Dec 6 19:30:37 2019 New Revision: 279061 URL: https://gcc.gnu.org/viewcvs?rev=279061&root=gcc&view=rev Log: 2019-12-06 Andreas Krebbel Vladimir Makarov

[Bug rtl-optimization/92176] LRA problem with reloads for subreg operands

2019-12-04 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92176 --- Comment #6 from Vladimir Makarov --- (In reply to Vladimir Makarov from comment #5) > > I'll investigate this problem more. Hi, Andreas. The rtlanal code (!lra_in_progress) was added to GCC since the first patch introducing LRA. As I wrot

[Bug rtl-optimization/92176] LRA problem with reloads for subreg operands

2019-12-02 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92176 --- Comment #5 from Vladimir Makarov --- (In reply to Andreas Krebbel from comment #3) > 276.ira: > > > /* Give the backend a chance to disallow the mode change. */ > if (GET_MODE_CLASS (xmode) != MODE_COMPLEX_INT > && GET_MODE_

[Bug rtl-optimization/92283] [10 Regression] 454.calculix miscomparison since r276645 with -O2 -march=znver2

2019-11-29 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92283 --- Comment #27 from Vladimir Makarov --- Author: vmakarov Date: Fri Nov 29 22:04:21 2019 New Revision: 278865 URL: https://gcc.gnu.org/viewcvs?rev=278865&root=gcc&view=rev Log: 2019-11-29 Vladimir Makarov PR rtl-optimization/92283

[Bug rtl-optimization/92283] [10 Regression] 454.calculix miscomparison since r276645 with -O2 -march=znver2

2019-11-29 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92283 --- Comment #26 from Vladimir Makarov --- I think I find the problem root. We have ** Local #2: ** Choosing alt 0 in insn 1804: (0) =v (1) %0 (2) vm (3) v {*fma_fmadd_df} Creating newreg=4707 from oldreg=1801,

[Bug rtl-optimization/90007] [9/10 Regression] ICE in extract_constrain_insn_cached, at recog.c:2223

2019-11-27 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90007 --- Comment #14 from Vladimir Makarov --- (In reply to Segher Boessenkool from comment #13) > Does that work? You cannot put all hard registers in memory I think? > Or do we require that and it is just not documented? It depends on insns. For

[Bug rtl-optimization/90007] [9/10 Regression] ICE in extract_constrain_insn_cached, at recog.c:2223

2019-11-27 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90007 --- Comment #12 from Vladimir Makarov --- Author: vmakarov Date: Wed Nov 27 14:24:47 2019 New Revision: 278770 URL: https://gcc.gnu.org/viewcvs?rev=278770&root=gcc&view=rev Log: 2019-11-27 Vladimir Makarov PR rtl-optimization/90007

[Bug rtl-optimization/92283] [10 Regression] 454.calculix miscomparison since r276645 with -O2 -march=znver2

2019-11-27 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92283 --- Comment #24 from Vladimir Makarov --- (In reply to Richard Biener from comment #23) > Vladimir, can you look into this LRA inheritance issue? Yes, I've started to work on this. I can not reproduce it on the current trunk. But yesterday, I'

[Bug ipa/44563] GCC uses a lot of RAM when compiling a large numbers of functions

2019-11-22 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=44563 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/90007] [9/10 Regression] ICE in extract_constrain_insn_cached, at recog.c:2223

2019-11-18 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90007 --- Comment #11 from Vladimir Makarov --- (In reply to Alexander Monakov from comment #4) > Well, often sel-sched just does not discriminate hardregs and pseudos when > checking if renaming/substitution may be applied. Sure, as a matter of > effi

[Bug rtl-optimization/91430] ICE in curr_insn_transform, at lra-constraints.c:3962

2019-08-14 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91430 --- Comment #2 from Vladimir Makarov --- (In reply to Martin Liška from comment #1) > Fixed on trunk with r273357, thus probably a dup of PR91102. > Vladimir? Yes, it is definitely a dup.

[Bug rtl-optimization/91223] [10 Regression] ICE: in curr_insn_transform, at lra-constraints.c:4459

2019-07-25 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91223 --- Comment #7 from Vladimir Makarov --- Author: vmakarov Date: Thu Jul 25 18:36:52 2019 New Revision: 273810 URL: https://gcc.gnu.org/viewcvs?rev=273810&root=gcc&view=rev Log: 2019-07-25 Vladimir Makarov PR rtl-optimization/91223

[Bug rtl-optimization/91223] [10 Regression] ICE: in curr_insn_transform, at lra-constraints.c:4459

2019-07-24 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91223 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug target/91102] [9/10 Regression] aarch64 ICE on Linux kernel with -Os starting with r270266

2019-07-10 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91102 --- Comment #7 from Vladimir Makarov --- Author: vmakarov Date: Wed Jul 10 16:07:10 2019 New Revision: 273357 URL: https://gcc.gnu.org/viewcvs?rev=273357&root=gcc&view=rev Log: 2019-07-10 Vladimir Makarov PR target/91102 * lr

[Bug target/91102] [9/10 Regression] aarch64 ICE on Linux kernel with -Os starting with r270266

2019-07-07 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91102 --- Comment #5 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #1) > > Vlad, could you please have a look? The culprit patch is actually https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=265942 Prohibiting reload for

[Bug rtl-optimization/90976] A suspicious code in lra.c since r177852

2019-06-26 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90976 --- Comment #2 from Vladimir Makarov --- (In reply to Jeffrey A. Law from comment #1) > Agreed, looks suspicious. From my reading of the code, I think using > "constraints" rather than "recog_data.constraints" is correct. > > The prior call to

[Bug rtl-optimization/88751] Performance regression reload vs lra

2019-06-01 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88751 --- Comment #5 from Vladimir Makarov --- (In reply to Andreas Krebbel from comment #4) > (In reply to Babneet Singh from comment #3) > > Hi Andreas and Richard: What's the status for this issue? Which approach > > will be used to resolve this iss

[Bug rtl-optimization/90174] Bad register spill due to top-down allocation order

2019-05-03 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90174 --- Comment #4 from Vladimir Makarov --- (In reply to Feng Xue from comment #0) > Current regional RA uses a top-down allocation order, which may not properly > split a long live range that crosses sub-region with high register pressure. > > In

[Bug rtl-optimization/87871] [9 Regression] testcases fail after r265398 on arm

2019-04-14 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87871 --- Comment #25 from Vladimir Makarov --- (In reply to Peter Bergner from comment #24) > So improve_allocation() initially looks at using r0, but disregards it > because check_hard_reg_p() returns false for r0, and that is because we fail > this

[Bug rtl-optimization/87871] [9 Regression] testcases fail after r265398 on arm

2019-04-12 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87871 --- Comment #20 from Vladimir Makarov --- (In reply to Wilco from comment #19) > (In reply to Peter Bergner from comment #18) > > (In reply to Segher Boessenkool from comment #15) > > > Popping a5(r116,l0) -- assign reg 3 > > > Poppi

[Bug rtl-optimization/89865] [9 Regression] FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45

2019-04-01 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89865 --- Comment #22 from Vladimir Makarov --- Author: vmakarov Date: Mon Apr 1 16:18:30 2019 New Revision: 270060 URL: https://gcc.gnu.org/viewcvs?rev=270060&root=gcc&view=rev Log: 2019-04-01 Vladimir Makarov PR rtl-optimization/89865

[Bug rtl-optimization/89865] [9 Regression] FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45

2019-03-29 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89865 --- Comment #20 from Vladimir Makarov --- I'll be working on this.

[Bug rtl-optimization/89676] [7/8/9 Regression] Redundant moves for long long shift on 32bit x86

2019-03-25 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89676 --- Comment #9 from Vladimir Makarov --- Author: vmakarov Date: Mon Mar 25 21:14:40 2019 New Revision: 269924 URL: https://gcc.gnu.org/viewcvs?rev=269924&root=gcc&view=rev Log: 2019-03-25 Vladimir Makarov PR rtl-optimization/89676

[Bug rtl-optimization/89676] [7/8/9 Regression] Redundant moves for long long shift on 32bit x86

2019-03-22 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89676 --- Comment #8 from Vladimir Makarov --- Author: vmakarov Date: Fri Mar 22 16:59:21 2019 New Revision: 269878 URL: https://gcc.gnu.org/viewcvs?rev=269878&root=gcc&view=rev Log: 2019-03-22 Vladimir Makarov PR rtl-optimization/89676

[Bug rtl-optimization/89676] [7/8/9 Regression] Redundant moves for long long shift on 32bit x86

2019-03-20 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89676 --- Comment #7 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #6) > > That said, if you can handle it in the RA, it could handle even those > variable shift cases better (just make sure it doesn't overlap ecx, but > otherwise

[Bug rtl-optimization/89676] [7/8/9 Regression] Redundant moves for long long shift on 32bit x86

2019-03-20 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89676 --- Comment #5 from Vladimir Makarov --- I am working on it. It is a non-trivial problem. We should somehow exclude creation of conflicts in lra-lives.c for an early clobber matched with an input. I hope to fix it this week.

[Bug target/85860] [8/9 Regression] ICE: in lra_split_hard_reg_for, at lra-assigns.c:1810: unable to find a register to spill with -flive-range-shrinkage -mbmi2

2019-03-13 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85860 --- Comment #7 from Vladimir Makarov --- Author: vmakarov Date: Wed Mar 13 20:44:50 2019 New Revision: 269663 URL: https://gcc.gnu.org/viewcvs?rev=269663&root=gcc&view=rev Log: 2019-03-13 Vladimir Makarov PR target/85860 * lr

[Bug target/85860] [8/9 Regression] ICE: in lra_split_hard_reg_for, at lra-assigns.c:1810: unable to find a register to spill with -flive-range-shrinkage -mbmi2

2019-03-13 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85860 --- Comment #6 from Vladimir Makarov --- Author: vmakarov Date: Wed Mar 13 20:35:18 2019 New Revision: 269662 URL: https://gcc.gnu.org/viewcvs?rev=269662&root=gcc&view=rev Log: 2019-03-13 Vladimir Makarov PR target/85860 * lr

[Bug rtl-optimization/87716] [9 Regression] FAIL: gcc.target/i386/pr57193.c scan-assembler-times movdqa 2

2019-03-01 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87716 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/88596] [9 Regression] ICE: Maximum number of LRA assignment passes is achieved (30)

2019-03-01 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88596 --- Comment #8 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #7) > The above testcase reproduced, reduced to following, started with r266385. > Note, this testcase ICEd in gcc 7.x and earlier too, got fixed with r258504 > (sta

[Bug target/89271] [9 Regression] gcc.target/powerpc/vsx-simode2.c stopped working in GCC 9

2019-02-20 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89271 --- Comment #11 from Vladimir Makarov --- (In reply to Alan Modra from comment #5) > Created attachment 45760 [details] > Current set of patches > > It turns out there is a lot more than just wrong register_move_cost. This > patchset does fix t

[Bug rtl-optimization/89271] gcc.target/powerpc/vsx-simode2.c stopped working in GCC 9

2019-02-13 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89271 --- Comment #1 from Vladimir Makarov --- > This is because IRA does > > r125: preferred NO_REGS, alternative NO_REGS, allocno NO_REGS > >a1(r125,l0) costs: BASE_REGS:14004,14004 GENERAL_REGS:14004,14004- >LINK_REGS:24010,24010 CTR

[Bug middle-end/88560] [9 Regression] armv8_2-fp16-move-1.c and related regressions after r266385

2019-02-08 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88560 --- Comment #13 from Vladimir Makarov --- Author: vmakarov Date: Fri Feb 8 19:01:10 2019 New Revision: 268705 URL: https://gcc.gnu.org/viewcvs?rev=268705&root=gcc&view=rev Log: 2019-02-08 Vladimir Makarov PR middle-end/88560

[Bug rtl-optimization/89225] [9 Regression] LRA hang on ppc64le compiling glibc starting with r268404

2019-02-06 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89225 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Wed Feb 6 21:48:45 2019 New Revision: 268597 URL: https://gcc.gnu.org/viewcvs?rev=268597&root=gcc&view=rev Log: 2019-02-06 Vladimir Makarov PR rtl-optimization/89225

[Bug rtl-optimization/89225] [9 Regression] LRA hang on ppc64le compiling glibc starting with r268404

2019-02-06 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89225 --- Comment #1 from Vladimir Makarov --- It seems my latest patch for PR87246 caused this: https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=268404

[Bug target/86487] [7/8/9 Regression] insn does not satisfy its constraints on arm big-endian

2019-01-31 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86487 --- Comment #11 from Vladimir Makarov --- (In reply to avieira from comment #10) > Hi Vlad, > > I don't think it is a duplication. Sorry, I was not clear. My comment relates to test #include int32x2_t b(long c, ...) {} $ arm-none-eabi-gcc -

[Bug rtl-optimization/88296] [9 Regression] Infinite loop in lra_split_hard_reg_for

2019-01-31 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88296 --- Comment #5 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #3) > for Vlad the question > is just whether r266862 is a real fix or just made it latent. Given that > both are IRA costs changes, I assume it is a real fix. I'v

[Bug rtl-optimization/88596] [9 Regression] ICE: Maximum number of LRA assignment passes is achieved (30)

2019-01-31 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88596 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug target/86487] [7/8/9 Regression] insn does not satisfy its constraints on arm big-endian

2019-01-31 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86487 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/87246] [7/8/9 Regression] ICE in decompose_normal_address, at rtlanal.c:6379

2019-01-30 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87246 --- Comment #7 from Vladimir Makarov --- Author: vmakarov Date: Wed Jan 30 21:49:23 2019 New Revision: 268404 URL: https://gcc.gnu.org/viewcvs?rev=268404&root=gcc&view=rev Log: 2019-01-30 Vladimir Makarov PR rtl-optimization/87246

[Bug rtl-optimization/87246] [7/8/9 Regression] ICE in decompose_normal_address, at rtlanal.c:6379

2019-01-30 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87246 --- Comment #6 from Vladimir Makarov --- I am working on this. I hope to fix the PR this week.

[Bug rtl-optimization/88846] [9 Regression] pr69776-2.c failure on 32 bit AIX

2019-01-25 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88846 --- Comment #6 from Vladimir Makarov --- Sorry, I wrote wrong PR number in the ChangeLog entry (I already fix the number). Here is the info about the patch I've committed Author: vmakarov Date: Fri Jan 25 22:13:43 2019 New Revision: 268280 URL

[Bug rtl-optimization/88846] [9 Regression] pr69776-2.c failure on 32 bit AIX

2019-01-23 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88846 --- Comment #5 from Vladimir Makarov --- There should be no REG_EQUIV as RTL doc says "it is valid for the compiler to replace the pseudo-register by stack slot throughout the function". In this case the substitution results in a wrong code.

[Bug middle-end/88560] [9 Regression] armv8_2-fp16-move-1.c and related regressions after r266385

2019-01-21 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88560 --- Comment #9 from Vladimir Makarov --- (In reply to Vladimir Makarov from comment #8) > Created attachment 45485 [details] > Proposed patch Does this patch solves the problem?

[Bug middle-end/88560] [9 Regression] armv8_2-fp16-move-1.c and related regressions after r266385

2019-01-21 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88560 --- Comment #8 from Vladimir Makarov --- Created attachment 45485 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=45485&action=edit Proposed patch

[Bug target/88850] [9 Regression] Hard register coming out of expand causing reload to fail.

2019-01-21 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88850 --- Comment #6 from Vladimir Makarov --- (In reply to Tamar Christina from comment #5) > So yeah it seems that there are three issues here: > > 1) We should probably have an r -> r alternative for *neon_mov. > 2) The costs are now flipped from w

[Bug middle-end/88560] [9 Regression] armv8_2-fp16-move-1.c and related regressions after r266385

2019-01-21 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88560 --- Comment #7 from Vladimir Makarov --- (In reply to Wilco from comment #6) > (In reply to Vladimir Makarov from comment #5) > > We have too many tests checking expected generated code. We should more > > focus on overall effect of the change.

[Bug rtl-optimization/87763] [9 Regression] aarch64 target testcases fail after r265398

2019-01-21 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87763 --- Comment #14 from Vladimir Makarov --- I've checked cvtf_1.c generated code and I don't see additional fmov anymore. I guess it was fixed by an ira-costs.c change (a special consideration of moves containing hard regs). I think this PR is

[Bug middle-end/88560] [9 Regression] armv8_2-fp16-move-1.c and related regressions after r266385

2019-01-18 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88560 --- Comment #5 from Vladimir Makarov --- We have too many tests checking expected generated code. We should more focus on overall effect of the change. SPEC would be a good criterium although it is hard to check SPEC for each patch. I've check

[Bug rtl-optimization/87305] [9 Regression] Segfault in end_hard_regno in setup_live_pseudos_and_spill_after_risky_transforms on aarch64 big-endian

2019-01-11 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87305 --- Comment #6 from Vladimir Makarov --- Author: vmakarov Date: Fri Jan 11 19:25:31 2019 New Revision: 267854 URL: https://gcc.gnu.org/viewcvs?rev=267854&root=gcc&view=rev Log: 2019-01-11 Vladimir Makarov PR rtl-optimization/87305

[Bug rtl-optimization/87305] [9 Regression] Segfault in end_hard_regno in setup_live_pseudos_and_spill_after_risky_transforms on aarch64 big-endian

2019-01-10 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87305 --- Comment #4 from Vladimir Makarov --- Author: vmakarov Date: Thu Jan 10 21:02:50 2019 New Revision: 267823 URL: https://gcc.gnu.org/viewcvs?rev=267823&root=gcc&view=rev Log: 2019-01-10 Vladimir Makarov PR rtl-optimization/87305

[Bug rtl-optimization/87305] [9 Regression] Segfault in end_hard_regno in setup_live_pseudos_and_spill_after_risky_transforms on aarch64 big-endian

2019-01-08 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87305 --- Comment #3 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #2) > > Vlad, could you please have a look? I've just started to work on it.

[Bug target/88457] ICE: Max. number of generated reload insns per insn is achieved (90)

2018-12-20 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88457 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Thu Dec 20 18:07:51 2018 New Revision: 267307 URL: https://gcc.gnu.org/viewcvs?rev=267307&root=gcc&view=rev Log: 2018-12-20 Vladimir Makarov PR target/88457 * ir

[Bug rtl-optimization/87759] [8/9 Regression] ICE in lra_assign, at lra-assigns.c:1624, or ICE: Maximum number of LRA assignment passes is achieved (30), or compile-time hog

2018-12-18 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87759 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Tue Dec 18 21:20:16 2018 New Revision: 267244 URL: https://gcc.gnu.org/viewcvs?rev=267244&root=gcc&view=rev Log: 2018-12-18 Vladimir Makarov PR rtl-optimization/87759

[Bug rtl-optimization/87759] [8/9 Regression] ICE in lra_assign, at lra-assigns.c:1624, or ICE: Maximum number of LRA assignment passes is achieved (30), or compile-time hog

2018-12-14 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87759 --- Comment #2 from Vladimir Makarov --- I've started to work on it. The patch will be probably ready on Monday or Tuesday.

[Bug rtl-optimization/88414] [9 Regression] ICE in lra_assign, at lra-assigns.c:1624

2018-12-13 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88414 --- Comment #5 from Vladimir Makarov --- Author: vmakarov Date: Thu Dec 13 20:54:27 2018 New Revision: 267109 URL: https://gcc.gnu.org/viewcvs?rev=267109&root=gcc&view=rev Log: 2018-12-13 Vladimir Makarov PR rtl-optimization/88414

[Bug rtl-optimization/88414] [9 Regression] ICE in lra_assign, at lra-assigns.c:1624

2018-12-13 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88414 --- Comment #4 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #3) > Started with r257077. In any case, it seems to be a LRA error-recovery bug. > We first properly diagnose that the inline asm has constraints that are > imposs

[Bug target/88457] ICE: Max. number of generated reload insns per insn is achieved (90)

2018-12-13 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88457 --- Comment #2 from Vladimir Makarov --- (In reply to Richard Biener from comment #1) > ira-max-conflict-table-size=0 might be an impossible value - Vlad? Any size is possible. Simply in this case conflict table is not built and simple RA (ki

[Bug rtl-optimization/88349] [9 regression][MIPS] Redundant store instructions generated start with r266385

2018-12-07 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88349 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Fri Dec 7 16:08:17 2018 New Revision: 266894 URL: https://gcc.gnu.org/viewcvs?rev=266894&root=gcc&view=rev Log: 2018-12-07 Vladimir Makarov PR rtl-optimization/88349

[Bug target/88282] [9 Regression] ICE in df_install_refs at gcc/df-scan.c:2379

2018-12-06 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88282 --- Comment #9 from Vladimir Makarov --- Author: vmakarov Date: Thu Dec 6 18:41:46 2018 New Revision: 266862 URL: https://gcc.gnu.org/viewcvs?rev=266862&root=gcc&view=rev Log: 2018-12-06 Vladimir Makarov PR target/88282 * ir

[Bug rtl-optimization/88317] ICE: Segmentation fault (in split_reg -> bitmap_set_bit -> bitmap_list_link_element)

2018-12-04 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88317 --- Comment #4 from Vladimir Makarov --- Author: vmakarov Date: Tue Dec 4 22:50:14 2018 New Revision: 266803 URL: https://gcc.gnu.org/viewcvs?rev=266803&root=gcc&view=rev Log: 2018-12-04 Vladimir Makarov PR rtl-optimization/88317

[Bug rtl-optimization/88317] ICE: Segmentation fault (in split_reg -> bitmap_set_bit -> bitmap_list_link_element)

2018-12-04 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88317 --- Comment #3 from Vladimir Makarov --- (In reply to Richard Biener from comment #1) > Vlad - can you look into the above? There's also lra_split_regs set > (and maybe others) which will have similar problems. The following should > make it e

[Bug target/88282] [9 Regression] ICE in df_install_refs at gcc/df-scan.c:2379

2018-12-04 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88282 --- Comment #7 from Vladimir Makarov --- Author: vmakarov Date: Tue Dec 4 15:10:46 2018 New Revision: 266784 URL: https://gcc.gnu.org/viewcvs?rev=266784&root=gcc&view=rev Log: 2018-12-04 Vladimir Makarov PR target/88282 * ir

[Bug rtl-optimization/88179] [9 regression][MIPS] pr84941.c ICE in lra_eliminate_reg_if_possible at lra-eliminations.c:1393 start with r266385

2018-11-30 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88179 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Fri Nov 30 20:15:56 2018 New Revision: 266682 URL: https://gcc.gnu.org/viewcvs?rev=266682&root=gcc&view=rev Log: 2018-11-30 Vladimir Makarov PR rtl-optimization/88179

[Bug target/88282] ICE in df_install_refs at gcc/df-scan.c:2379

2018-11-30 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88282 --- Comment #4 from Vladimir Makarov --- (In reply to Tamar Christina from comment #3) > This is caused by the change in r266385 for PR87718. > > That causes the cost model to go completely off the rail and also changes > the register classes. >

[Bug target/88207] [9 regression] gcc.target/i386/pr22076.c etc. FAIL

2018-11-28 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88207 --- Comment #4 from Vladimir Makarov --- Author: vmakarov Date: Wed Nov 28 20:08:03 2018 New Revision: 266582 URL: https://gcc.gnu.org/viewcvs?rev=266582&root=gcc&view=rev Log: 2018-11-28 Vladimir Makarov PR target/88207 * ir

[Bug rtl-optimization/88179] [9 regression][MIPS] pr84941.c ICE in lra_eliminate_reg_if_possible at lra-eliminations.c:1393 start with r266385

2018-11-28 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88179 --- Comment #1 from Vladimir Makarov --- Thank you for reporting this. I am working on the PR. I think the solution will be ready on this week.

[Bug target/88207] [9 regression] gcc.target/i386/pr22076.c etc. FAIL

2018-11-26 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88207 --- Comment #3 from Vladimir Makarov --- Thank you for reporting it. I've started to work on the PR. I'll keep you informed about the progress.

[Bug bootstrap/88157] [9 Regression] ICE when building libgo encoding/gob.lo starting with r266385

2018-11-24 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88157 --- Comment #8 from Vladimir Makarov --- Author: vmakarov Date: Sun Nov 25 05:46:44 2018 New Revision: 266435 URL: https://gcc.gnu.org/viewcvs?rev=266435&root=gcc&view=rev Log: 2018-11-25 Vladimir Makarov PR bootstrap/88157 *

[Bug bootstrap/88157] [9 Regression] ICE when building libgo encoding/gob.lo starting with r266385

2018-11-23 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88157 --- Comment #6 from Vladimir Makarov --- Author: vmakarov Date: Fri Nov 23 22:00:43 2018 New Revision: 266422 URL: https://gcc.gnu.org/viewcvs?rev=266422&root=gcc&view=rev Log: 2018-11-23 Vladimir Makarov PR bootstrap/88157 *

[Bug rtl-optimization/87485] [9 Regression] Compile time hog w/ -O2 -fschedule-insns -fno-guess-branch-probability -fno-isolate-erroneous-paths-dereference -fno-omit-frame-pointer -fno-split-wide-type

2018-11-22 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87485 --- Comment #18 from Vladimir Makarov --- (In reply to Vladimir Makarov from comment #17) > I've reproduced it. Clearly, it is some bug in LRA conflict calculation. > I will be working on it. I investigated it more. Before scheduling we hav

[Bug bootstrap/88157] [9 Regression] ICE when building libgo encoding/gob.lo starting with r266385

2018-11-22 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88157 --- Comment #3 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #2) > Note, no need to revert if it is something that can be resolved within a few > days, I can just exclude go from the enabled languages till then. OK, thanks.

[Bug rtl-optimization/87718] [9 Regression] FAIL: gcc.target/i386/avx512dq-concatv2si-1.c

2018-11-22 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87718 --- Comment #7 from Vladimir Makarov --- Author: vmakarov Date: Thu Nov 22 17:25:57 2018 New Revision: 266385 URL: https://gcc.gnu.org/viewcvs?rev=266385&root=gcc&view=rev Log: 2018-11-22 Vladimir Makarov PR rtl-optimization/87718

[Bug target/84757] [7/8/9 Regression] Useless MOVs and PUSHes to store results of MUL

2018-11-22 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84757 --- Comment #7 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #6) > Vlad, is this something that can be still done for GCC 9 or should we defer > to GCC 10? Adding live analysis on subreg level to LRA is a big work and I thi

[Bug rtl-optimization/87485] [9 Regression] Compile time hog w/ -O2 -fschedule-insns -fno-guess-branch-probability -fno-isolate-erroneous-paths-dereference -fno-omit-frame-pointer -fno-split-wide-type

2018-11-21 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87485 --- Comment #17 from Vladimir Makarov --- I've reproduced it. Clearly, it is some bug in LRA conflict calculation. I will be working on it.

[Bug rtl-optimization/87718] [9 Regression] FAIL: gcc.target/i386/avx512dq-concatv2si-1.c

2018-11-19 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87718 --- Comment #6 from Vladimir Makarov --- The culprit for the bad code generation is the following insn description (define_insn "*movsi_internal" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m ,*y,*y,?*y,?m,?r,?*y,*v,*v,*v,m ,?r,?*

[Bug rtl-optimization/87718] [9 Regression] FAIL: gcc.target/i386/avx512dq-concatv2si-1.c

2018-11-14 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87718 --- Comment #5 from Vladimir Makarov --- In general moving from propagation of hard regs is good thing for RA. Although there are exception as this PR. The problem starts with IRA. It decides that r91 should be a general regs based on cos

[Bug rtl-optimization/78127] [6 Regression] AArch64 internal compiler error: in lra_eliminate, at lra-eliminations.c:1440

2018-10-17 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78127 --- Comment #7 from Vladimir Makarov --- (In reply to Wilco from comment #6) > (In reply to Vladimir Makarov from comment #3) > > Author: vmakarov > > Date: Thu Feb 16 19:47:15 2017 > > New Revision: 245514 > > > > URL: https://gcc.gnu.org/viewc

[Bug target/86547] s390x: Maximum number of LRA assignment passes is achieved (30) when compiling a small inline assembler snippet

2018-07-27 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86547 --- Comment #6 from Vladimir Makarov --- (In reply to Ilya Leoshkevich from comment #5) > > > Vladimir, could you please take a look at the attached patch? I > ran regression with and without it on x86_64, and compare_tests did not > show any n

[Bug rtl-optimization/79916] ICE in Max. number of generated reload insns per insn is achieved (90)

2018-04-13 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79916 --- Comment #10 from Vladimir Makarov --- Author: vmakarov Date: Fri Apr 13 22:55:16 2018 New Revision: 259379 URL: https://gcc.gnu.org/viewcvs?rev=259379&root=gcc&view=rev Log: 2018-04-13 Vladimir Makarov PR rtl-optimization/79916

[Bug rtl-optimization/79916] ICE in Max. number of generated reload insns per insn is achieved (90)

2018-04-12 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79916 --- Comment #9 from Vladimir Makarov --- I've reproduced one test bug on my machine by using: ./cc1 -I. ../../gcc/gcc/testsuite/gcc.dg/dfp/pr41049.c -fno-expensive-optimizations --param ira-max-conflict-table-size=0 -mpopcntd -O3 I think the fi

[Bug middle-end/85090] [8 Regression] wrong code with -O2 -fno-tree-dominator-opts -mavx512f -fira-algorithm=priority

2018-04-06 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85090 --- Comment #13 from Vladimir Makarov --- (In reply to Uroš Bizjak from comment #11) > (In reply to Jakub Jelinek from comment #5) > > I guess it depends on what exactly a normal subreg on lhs means. > > The documentation says: > > When

[Bug middle-end/85090] [8 Regression] wrong code with -O2 -fno-tree-dominator-opts -mavx512f -fira-algorithm=priority

2018-04-05 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85090 --- Comment #10 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #5) > I guess it depends on what exactly a normal subreg on lhs means. > The documentation says: > When used as an lvalue, 'subreg' is a word-based access

[Bug middle-end/67486] ira-color.c sanitizer detects signed integer overflow

2018-04-05 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67486 --- Comment #7 from Vladimir Makarov --- (In reply to David Binderman from comment #6) > I wonder if changing type of static array full_costs from int to long would > help solve the problem. > > Adding vmakarov, who seems to be the author of mos

[Bug inline-asm/84985] [6/7/8 Regression] ICE in match_reload, at lra-constraints.c:1068

2018-03-29 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84985 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Thu Mar 29 18:29:12 2018 New Revision: 258961 URL: https://gcc.gnu.org/viewcvs?rev=258961&root=gcc&view=rev Log: 2018-03-29 Vladimir Makarov PR inline-asm/84985

[Bug rtl-optimization/85072] g++ -O1 consumes all memory

2018-03-26 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85072 --- Comment #4 from Vladimir Makarov --- (In reply to Richard Biener from comment #3) > Doing a more "correct" patch like below shows that nearly all possible > "starts" are covered: > > (gdb) p bitmap_count_bits(starts) > $2 = 500039 > (gdb) p

[Bug inline-asm/85030] [6/7/8 Regression] internal compiler error: Floating point exception (validate_subreg())

2018-03-23 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85030 --- Comment #5 from Vladimir Makarov --- Author: vmakarov Date: Fri Mar 23 19:31:00 2018 New Revision: 258820 URL: https://gcc.gnu.org/viewcvs?rev=258820&root=gcc&view=rev Log: 2018-03-23 Vladimir Makarov PR inline-asm/85030

[Bug inline-asm/85030] [6/7/8 Regression] internal compiler error: Floating point exception (validate_subreg())

2018-03-22 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85030 --- Comment #4 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #3) > Trying to create BLKmode subreg of something (or subreg from BLKmode) is not > going to work well, but don't know the LRA code enough to know how to safely > g

[Bug target/84876] [8 Regression] ICE on invalid code in lra_assign at gcc/lra-assigns.c:1601 since r258504

2018-03-16 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84876 --- Comment #4 from Vladimir Makarov --- Author: vmakarov Date: Fri Mar 16 18:48:26 2018 New Revision: 258602 URL: https://gcc.gnu.org/viewcvs?rev=258602&root=gcc&view=rev Log: 2018-03-16 Vladimir Makarov PR target/84876 * lr

[Bug target/84876] [8 Regression] ICE on invalid code in lra_assign at gcc/lra-assigns.c:1601 since r258504

2018-03-15 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84876 --- Comment #3 from Vladimir Makarov --- (In reply to Vladimir Makarov from comment #2) > Sorry, my bad. It is easy to fix. I think the patch will be ready today. Unfortunately, this test also triggers more serious problem of my last patch (r2

[Bug target/84876] [8 Regression] ICE on invalid code in lra_assign at gcc/lra-assigns.c:1601 since r258504

2018-03-15 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84876 --- Comment #2 from Vladimir Makarov --- Sorry, my bad. It is easy to fix. I think the patch will be ready today.

[Bug target/84757] [7/8 Regression] Useless MOVs and PUSHes to store results of MUL

2018-03-14 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84757 --- Comment #4 from Vladimir Makarov --- Sorry, the analysis took more time than I thought. This PR can be solved only by introducing live range analysis in LRA on **subreg level**. IRA already has such analysis and therefore it makes such allo

[Bug target/83712] [6/7 Regression] "Unable to find a register to spill" when compiling for thumb1

2018-03-13 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83712 --- Comment #11 from Vladimir Makarov --- Author: vmakarov Date: Tue Mar 13 20:42:49 2018 New Revision: 258504 URL: https://gcc.gnu.org/viewcvs?rev=258504&root=gcc&view=rev Log: 2018-03-13 Vladimir Makarov PR target/83712 * l

[Bug target/83712] [6/7 Regression] "Unable to find a register to spill" when compiling for thumb1

2018-03-10 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83712 --- Comment #10 from Vladimir Makarov --- Author: vmakarov Date: Sat Mar 10 16:32:21 2018 New Revision: 258415 URL: https://gcc.gnu.org/viewcvs?rev=258415&root=gcc&view=rev Log: 2018-03-10 Vladimir Makarov Reverting patch: 20

[Bug target/84757] [7/8 Regression] Useless MOVs and PUSHes to store results of MUL

2018-03-09 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84757 --- Comment #3 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #2) > Started with r244942. Vlad, can you please have a look? Thanks. Sure, I'll look at this. Some analysis will be ready today.

[Bug target/83712] [6/7/8 Regression] "Unable to find a register to spill" when compiling for thumb1

2018-03-09 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83712 --- Comment #7 from Vladimir Makarov --- Author: vmakarov Date: Fri Mar 9 16:00:36 2018 New Revision: 258390 URL: https://gcc.gnu.org/viewcvs?rev=258390&root=gcc&view=rev Log: 2018-03-09 Vladimir Makarov PR target/83712 * lr

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