[Bug target/83712] [6/7/8 Regression] "Unable to find a register to spill" when compiling for thumb1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83712 --- Comment #6 from Vladimir Makarov --- I've decided to fix it in RA because it could help to fix analogous bugs when existing hard reg splitting code fails. This particular bug is more complicated because it happens for non-small reg class.

[Bug target/81572] [7 Regression] gcc-7 regression: unnecessary vector regmove on compare

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81572 --- Comment #6 from Vladimir Makarov --- (In reply to Peter Bergner from comment #5) > Thanks for fixing this Vlad! Since this is a GCC 7 regression, can we get > this back ported there too? If it would help, I can do the bootstrap, >

[Bug middle-end/52285] [6/7/8 Regression] libgcrypt _gcry_burn_stack slowdown

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=52285 --- Comment #21 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #20) > Vlad, your thoughts on this? Can it be done in LRA or postreload-gcse or > some other post-LRA pass (if they do have loops)? I don't think it can be done

[Bug target/84534] [8 regression] several powerpc test cases fail starting with r257915

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84534 --- Comment #3 from Vladimir Makarov --- Actually, it is not a failure. I believe it is an improvement. We have less move insns now. The easiest way to fix is to change the expected move insns to the current number. I'd prefer changing the

[Bug rtl-optimization/83327] Spilling into hard regs not taken into account in lra liveness analysis

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83327 --- Comment #10 from Vladimir Makarov --- Any news about the patch testing on MIPS. It would be nice to move forward with the PR.

[Bug target/81572] [7/8 Regression] gcc-7 regression: unnecessary vector regmove on compare

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81572 --- Comment #4 from Vladimir Makarov --- Author: vmakarov Date: Thu Feb 22 21:17:51 2018 New Revision: 257915 URL: https://gcc.gnu.org/viewcvs?rev=257915=gcc=rev Log: 2018-02-22 Vladimir Makarov PR target/81572

[Bug target/81572] [7/8 Regression] gcc-7 regression: unnecessary vector regmove on compare

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81572 --- Comment #3 from Vladimir Makarov --- I am working on this PR. The patch will be ready today or tomorrow. The problem is that the move insn has one alternative with early clobber and this move insn is processed on a fast path which

[Bug rtl-optimization/70023] [6/7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1417/8 with -fschedule-insns

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70023 --- Comment #13 from Vladimir Makarov --- Author: vmakarov Date: Fri Feb 16 18:17:09 2018 New Revision: 257751 URL: https://gcc.gnu.org/viewcvs?rev=257751=gcc=rev Log: 2018-02-16 Vladimir Makarov PR

[Bug rtl-optimization/70023] [6/7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1417/8 with -fschedule-insns

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70023 --- Comment #12 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #11) > Still ICEs with current trunk. LRA has a hard reg splitting. It was absent in reload. It decreased the number of 'unable to find a register to spill'

[Bug target/84359] [8 regression] gcc.target/i386/pr57193.c fail

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84359 --- Comment #1 from Vladimir Makarov --- Author: vmakarov Date: Tue Feb 13 14:57:17 2018 New Revision: 257628 URL: https://gcc.gnu.org/viewcvs?rev=257628=gcc=rev Log: 2018-02-13 Vladimir Makarov PR target/84359

[Bug rtl-optimization/57193] [6/7/8 Regression] suboptimal register allocation for SSE registers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57193 --- Comment #16 from Vladimir Makarov --- Author: vmakarov Date: Fri Feb 9 18:23:58 2018 New Revision: 257537 URL: https://gcc.gnu.org/viewcvs?rev=257537=gcc=rev Log: 2018-02-09 Vladimir Makarov PR

[Bug c/83390] valgrind error in lra_eliminate_regs_1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83390 --- Comment #8 from Vladimir Makarov --- (In reply to David Binderman from comment #0) > A build of today's gcc trunk with valgrind produces this: > > ==8995== Conditional jump or move depends on uninitialised value(s) > ==8995==at

[Bug target/82444] ICE in ira_init_register_move_cost, at ira.c:1581

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82444 --- Comment #1 from Vladimir Makarov --- Author: vmakarov Date: Wed Jan 31 19:03:11 2018 New Revision: 257254 URL: https://gcc.gnu.org/viewcvs?rev=257254=gcc=rev Log: 2018-01-31 Vladimir Makarov PR target/82444

[Bug target/84112] [8 Regression] powerpc64le ICE in LRA on openjdk

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84112 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Tue Jan 30 20:28:59 2018 New Revision: 257204 URL: https://gcc.gnu.org/viewcvs?rev=257204=gcc=rev Log: 2018-01-30 Vladimir Makarov PR target/84112

[Bug target/84112] [8 Regression] powerpc64le ICE in LRA on openjdk

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84112 --- Comment #1 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #0) > The following testcase ICEs with -mcpu=power8 -O3 -fstack-protector-strong > -fpic on powerpc64le-linux with: > rh1539812.i: In function ‘foo’: >

[Bug target/83712] [6/7/8 Regression] "Unable to find a register to spill" when compiling for thumb1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83712 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug target/84014] [6/7/8 Regression] ICE in setup_min_max_allocno_live_range_point, at ira-build.c:2762

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84014 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Wed Jan 24 19:45:55 2018 New Revision: 257029 URL: https://gcc.gnu.org/viewcvs?rev=257029=gcc=rev Log: 2018-01-24 Vladimir Makarov PR target/84014

[Bug target/84014] [6/7/8 Regression] ICE in setup_min_max_allocno_live_range_point, at ira-build.c:2762

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84014 --- Comment #2 from Vladimir Makarov --- Thank you for reporting. The problem occurs when only one subreg (obj) of register (allocno) is used in a function. I'll work on a patch.

[Bug rtl-optimization/83147] LRA inheritance undo on multiple sets problem

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83147 --- Comment #4 from Vladimir Makarov --- Author: vmakarov Date: Fri Jan 19 22:16:30 2018 New Revision: 256902 URL: https://gcc.gnu.org/viewcvs?rev=256902=gcc=rev Log: 2018-01-19 Andreas Krebbel PR

[Bug rtl-optimization/83147] LRA inheritance undo on multiple sets problem

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83147 Richard Biener changed: What|Removed |Added Keywords||ra --- Comment #2 from Vladimir

[Bug rtl-optimization/80481] Unoptimal additional copy instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80481 --- Comment #7 from Vladimir Makarov --- Author: vmakarov Date: Tue Jan 16 21:42:13 2018 New Revision: 256761 URL: https://gcc.gnu.org/viewcvs?rev=256761=gcc=rev Log: 2018-01-16 Vladimir Makarov PR

[Bug rtl-optimization/80481] Unoptimal additional copy instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80481 --- Comment #6 from Vladimir Makarov --- (In reply to Rainer Orth from comment #5) > Created attachment 43121 [details] > i386-pc-solaris2.11 -m64 assembler output Thank you for the code. The patch solves the problem for solaris too.

[Bug rtl-optimization/83620] [8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1470: unable to find a register to spill with -flive-range-shrinkage --param=max-sched-ready-insns=0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83620 --- Comment #6 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #4) > Or, alternatively, does --param=max-sched-ready-insns=0 make sense and is it > supportable? If not, we could just require it to be at least one. This

[Bug rtl-optimization/80481] Unoptimal additional copy instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80481 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Fri Jan 12 17:00:36 2018 New Revision: 256590 URL: https://gcc.gnu.org/viewcvs?rev=256590=gcc=rev Log: 2018-01-12 Vladimir Makarov PR

[Bug rtl-optimization/80481] Unoptimal additional copy instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80481 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug target/83399] Power8 ICE During LRA with 2-op rtl pattern for lvx instruction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83399 --- Comment #9 from Vladimir Makarov --- (In reply to Peter Bergner from comment #8) > Created attachment 43064 [details] > Proposed fix > > I'm testing the attached patch. Thank you, Peter. I thought about resurrection of address mutations

[Bug target/83399] Power8 ICE During LRA with 2-op rtl pattern for lvx instruction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83399 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/83317] [7/8 Regression] ICE in lra_eliminate_reg_if_possible compiling Python with -mfpmath=sse on x86 Linux

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83317 --- Comment #6 from Vladimir Makarov --- Author: vmakarov Date: Fri Dec 8 23:47:44 2017 New Revision: 255517 URL: https://gcc.gnu.org/viewcvs?rev=255517=gcc=rev Log: 2017-12-08 Vladimir Makarov PR

[Bug rtl-optimization/83317] [7/8 Regression] ICE in lra_eliminate_reg_if_possible compiling Python with -mfpmath=sse on x86 Linux

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83317 --- Comment #4 from Vladimir Makarov --- Eric, I think the patch caused the problem was intended for asm insns but it actually works on any insn. I guess constraining the original patch to asms could be a solution. I can make a patch and after

[Bug rtl-optimization/80818] LRA clobbers live hard reg clobbered during rematerialization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80818 --- Comment #12 from Vladimir Makarov --- Author: vmakarov Date: Thu Dec 7 17:50:54 2017 New Revision: 255471 URL: https://gcc.gnu.org/viewcvs?rev=255471=gcc=rev Log: 2017-12-07 Vladimir Makarov PR target/83252

[Bug target/83252] [8 Regression] Wrong code with "-march=skylake-avx512 -O3"

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83252 --- Comment #14 from Vladimir Makarov --- Author: vmakarov Date: Thu Dec 7 17:50:54 2017 New Revision: 255471 URL: https://gcc.gnu.org/viewcvs?rev=255471=gcc=rev Log: 2017-12-07 Vladimir Makarov PR target/83252

[Bug target/83252] [8 Regression] Wrong code with "-march=skylake-avx512 -O3"

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83252 --- Comment #13 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #12) > This broke again with r255377. > Testcase in patch form at > https://gcc.gnu.org/ml/gcc-patches/2017-12/msg00133.html I've started to work on it. In any

[Bug rtl-optimization/80818] LRA clobbers live hard reg clobbered during rematerialization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80818 --- Comment #11 from Vladimir Makarov --- I am still working on this PR. I hope to fix it on this week or on the next one (the patch will need a lot of testing).

[Bug rtl-optimization/80818] LRA clobbers live hard reg clobbered during rematerialization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80818 --- Comment #10 from Vladimir Makarov --- Author: vmakarov Date: Wed Nov 29 22:19:25 2017 New Revision: 255258 URL: https://gcc.gnu.org/viewcvs?rev=255258=gcc=rev Log: 2017-11-29 Vladimir Makarov PR

[Bug rtl-optimization/80818] LRA clobbers live hard reg clobbered during rematerialization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80818 --- Comment #9 from Vladimir Makarov --- (In reply to Andreas Krebbel from comment #8) > Hi Vladimir. What do you think about the additional patch? Andreas, sorry for the delay with the answer. The patch looks reasonable for me. If your

[Bug middle-end/82556] [7/8 Regression] internal compiler error in curr_insn_transform, at lra-constraints.c:4307

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82556 --- Comment #8 from Vladimir Makarov --- Author: vmakarov Date: Wed Oct 18 16:47:38 2017 New Revision: 253863 URL: https://gcc.gnu.org/viewcvs?rev=253863=gcc=rev Log: 2017-10-18 Vladimir Makarov PR

[Bug middle-end/82556] [7/8 Regression] internal compiler error in curr_insn_transform, at lra-constraints.c:4307

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82556 --- Comment #7 from Vladimir Makarov --- Author: vmakarov Date: Wed Oct 18 16:44:27 2017 New Revision: 253862 URL: https://gcc.gnu.org/viewcvs?rev=253862=gcc=rev Log: 2017-10-18 Vladimir Makarov PR

[Bug middle-end/82556] [7/8 Regression] internal compiler error in curr_insn_transform, at lra-constraints.c:4307

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82556 --- Comment #6 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #5) > Indeed started with my r253710. If there is something wrong on the > constraints on the patterns, please let me know. The constraints are ok. I'll probably

[Bug middle-end/82556] [7/8 Regression] internal compiler error in curr_insn_transform, at lra-constraints.c:4307

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82556 --- Comment #4 from Vladimir Makarov --- (In reply to Richard Biener from comment #3) > Confirmed on the branch (for the unreduced testcase). GCC 7.2 works. > > Probably Jakubs pattern changes. It is an unusual pattern for LRA. I guess it

[Bug sanitizer/82353] [8 Regression] runtime ubsan crash

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82353 --- Comment #10 from Vladimir Makarov --- Author: vmakarov Date: Mon Oct 16 20:34:53 2017 New Revision: 253796 URL: https://gcc.gnu.org/viewcvs?rev=253796=gcc=rev Log: 2017-10-16 Vladimir Makarov PR

[Bug sanitizer/82353] [8 Regression] runtime ubsan crash

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82353 --- Comment #8 from Vladimir Makarov --- Author: vmakarov Date: Thu Oct 12 17:06:29 2017 New Revision: 253685 URL: https://gcc.gnu.org/viewcvs?rev=253685=gcc=rev Log: 2017-10-12 Vladimir Makarov Revert

[Bug sanitizer/82353] [8 Regression] runtime ubsan crash

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82353 --- Comment #6 from Vladimir Makarov --- Author: vmakarov Date: Wed Oct 11 19:35:48 2017 New Revision: 253656 URL: https://gcc.gnu.org/viewcvs?rev=253656=gcc=rev Log: 2017-10-11 Vladimir Makarov PR

[Bug sanitizer/82353] [8 Regression] runtime ubsan crash

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82353 --- Comment #5 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #3) > Vlad, can you please have a look? I'll still try to see if we can have a > single file testcase here. Yes, it seems as LRA rematerialization bug. I'll

[Bug target/81481] [7/8 Regression] Spills %xmm to stack in glibc strspn SSE 4.2 variant

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81481 --- Comment #5 from Vladimir Makarov --- Author: vmakarov Date: Fri Sep 29 17:39:58 2017 New Revision: 253300 URL: https://gcc.gnu.org/viewcvs?rev=253300=gcc=rev Log: 2017-09-29 Vladimir Makarov PR target/81481

[Bug rtl-optimization/82338] valgrind error in inherit_in_ebb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82338 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Fri Sep 29 17:15:24 2017 New Revision: 253299 URL: https://gcc.gnu.org/viewcvs?rev=253299=gcc=rev Log: 2017-09-29 Vladimir Makarov PR

[Bug rtl-optimization/82338] valgrind error in inherit_in_ebb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82338 --- Comment #2 from Vladimir Makarov --- Thank you for reporting this, especially for reducing the test case. The bug is not dangerous, it does not result in wrong code generation but it might result in worse code. I reproduced it. It

[Bug target/81481] [7/8 Regression] Spills %xmm to stack in glibc strspn SSE 4.2 variant

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81481 --- Comment #4 from Vladimir Makarov --- In IRA we have (insn 9 8 24 2 (set (reg:V2DI 100 [ MEM[(const __m128i_u * {ref-all})_1] ]) (mem:V2DI (plus:SI (plus:SI (reg:SI 99 [ i ]) (reg:SI 87)) (const:SI

[Bug rtl-optimization/80818] LRA clobbers live hard reg clobbered during rematerialization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80818 --- Comment #6 from Vladimir Makarov --- Hi, Andreas. Could you check the patch I attached on your bigger test case. If it works, I will commit it.

[Bug rtl-optimization/80818] LRA clobbers live hard reg clobbered during rematerialization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80818 --- Comment #5 from Vladimir Makarov --- Created attachment 41686 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=41686=edit A proposed patch

[Bug rtl-optimization/80818] LRA clobbers live hard reg clobbered during rematerialization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80818 --- Comment #3 from Vladimir Makarov --- (In reply to Andreas Krebbel from comment #0) > Created attachment 41383 [details] > Experimental patch Andreas, thank you for working on the issue. You are right. The hard reg in the clobber should be

[Bug rtl-optimization/80754] [8 Regression][LRA] Invalid smull instruction generated in lra-remat

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80754 --- Comment #4 from Vladimir Makarov --- (In reply to Wilco from comment #3) > Patch here https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01364.html Thanks for working on the problem, Wilco. I'll review the patch and give you an answer on

[Bug rtl-optimization/80425] Extra inter-unit register move with zero-extension

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80425 --- Comment #2 from Vladimir Makarov --- We have the following fragment: 8: r96:DI=zero_extend(r93:SI) REG_DEAD r93:SI 13: r91:V8DI#0=r95:V16SI>>r96:DI REG_DEAD r96:DI REG_DEAD r95:V16SI IRA allocates general regs

[Bug rtl-optimization/77770] [5/6/7 Regression] Internal compiler error on source which compiles with earlier versions.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=0 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/80343] [7 Regression] ICE in extract_constrain_insn, at recog.c:2213 (error: insn does not satisfy its constraints)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80343 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Thu Apr 13 18:08:51 2017 New Revision: 246914 URL: https://gcc.gnu.org/viewcvs?rev=246914=gcc=rev Log: 2017-04-13 Vladimir Makarov PR

[Bug rtl-optimization/80343] [7 Regression] ICE in extract_constrain_insn, at recog.c:2213 (error: insn does not satisfy its constraints)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80343 --- Comment #2 from Vladimir Makarov --- I've reproduced it. It is a combination of scratches with rematerialization. I guess it will be fixed in a few days.

[Bug rtl-optimization/80352] Improper reload of operands with equiv pseudo

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80352 --- Comment #3 from Vladimir Makarov --- (In reply to Vladimir Makarov from comment #2) > Thank you for the report. I'll investigate the problem. A few hours ago > I've committed an additional patch. It might solve the problem. I'll check >

[Bug rtl-optimization/80352] Improper reload of operands with equiv pseudo

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80352 --- Comment #2 from Vladimir Makarov --- Thank you for the report. I'll investigate the problem. A few hours ago I've committed an additional patch. It might solve the problem. I'll check it.

[Bug rtl-optimization/70478] [LRA] S/390: Performance regression - superfluous stack frame

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70478 --- Comment #11 from Vladimir Makarov --- Author: vmakarov Date: Tue Apr 11 19:39:59 2017 New Revision: 246854 URL: https://gcc.gnu.org/viewcvs?rev=246854=gcc=rev Log: 2017-04-11 Vladimir Makarov PR

[Bug rtl-optimization/80352] Improper reload of operands with equiv pseudo

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80352 --- Comment #1 from Vladimir Makarov --- Thomas, it seems from your description the problem really exists. I tried to reproduce the problem with the test you provided but I've failed. I used today trunk. Could you provide more info (may be

[Bug rtl-optimization/70478] [LRA] S/390: Performance regression - superfluous stack frame

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70478 --- Comment #10 from Vladimir Makarov --- Author: vmakarov Date: Mon Apr 10 14:58:33 2017 New Revision: 246808 URL: https://gcc.gnu.org/viewcvs?rev=246808=gcc=rev Log: 2017-04-10 Vladimir Makarov PR

[Bug rtl-optimization/70478] [LRA] S/390: Performance regression - superfluous stack frame

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70478 --- Comment #9 from Vladimir Makarov --- Author: vmakarov Date: Sat Apr 8 19:18:42 2017 New Revision: 246789 URL: https://gcc.gnu.org/viewcvs?rev=246789=gcc=rev Log: 2017-04-08 Vladimir Makarov PR

[Bug rtl-optimization/70703] [6 regression] Regression in register usage on x86

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70703 --- Comment #15 from Vladimir Makarov --- Author: vmakarov Date: Fri Apr 7 16:06:28 2017 New Revision: 246765 URL: https://gcc.gnu.org/viewcvs?rev=246765=gcc=rev Log: 2017-04-07 Vladimir Makarov PR

[Bug rtl-optimization/70478] [LRA] S/390: Performance regression - superfluous stack frame

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70478 --- Comment #8 from Vladimir Makarov --- Author: vmakarov Date: Fri Apr 7 16:01:50 2017 New Revision: 246764 URL: https://gcc.gnu.org/viewcvs?rev=246764=gcc=rev Log: 2017-04-07 Vladimir Makarov PR

[Bug rtl-optimization/70478] [LRA] S/390: Performance regression - superfluous stack frame

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70478 --- Comment #7 from Vladimir Makarov --- (In reply to Andreas Krebbel from comment #6) > The only solution we found caused other regressions. I'll try to change the sensitive LRA code to solve it. It will need to test a few targets. So, if

[Bug rtl-optimization/70703] [6/7 regression] Regression in register usage on x86

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70703 --- Comment #13 from Vladimir Makarov --- Author: vmakarov Date: Wed Apr 5 16:14:28 2017 New Revision: 246711 URL: https://gcc.gnu.org/viewcvs?rev=246711=gcc=rev Log: 2017-04-05 Vladimir Makarov PR

[Bug rtl-optimization/70703] [6/7 regression] Regression in register usage on x86

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70703 --- Comment #12 from Vladimir Makarov --- Author: vmakarov Date: Wed Apr 5 15:07:51 2017 New Revision: 246707 URL: https://gcc.gnu.org/viewcvs?rev=246707=gcc=rev Log: 2017-04-05 Vladimir Makarov PR

[Bug rtl-optimization/70703] [6/7 regression] Regression in register usage on x86

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70703 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/80193] [7 Regression] ICE on valid (but hairy) C code at -O3 on x86_64-linux-gnu: in check_allocation, at ira.c:2563

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80193 --- Comment #6 from Vladimir Makarov --- Author: vmakarov Date: Tue Mar 28 20:55:38 2017 New Revision: 246554 URL: https://gcc.gnu.org/viewcvs?rev=246554=gcc=rev Log: 2017-03-28 Vladimir Makarov PR

[Bug rtl-optimization/80193] [7 Regression] ICE on valid (but hairy) C code at -O3 on x86_64-linux-gnu: in check_allocation, at ira.c:2563

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80193 --- Comment #5 from Vladimir Makarov --- The allocation is correct. Simply there is no rebuilding conflicts after generations moves on region edges (there are a lot of them, about 100) for LRA as LRA does not need the conflict info from IRA.

[Bug rtl-optimization/80193] [7 Regression] ICE on valid (but hairy) C code at -O3 on x86_64-linux-gnu: in check_allocation, at ira.c:2563

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80193 --- Comment #4 from Vladimir Makarov --- I've reproduced it and started to investigate. It is a very complicated example. I can not even say right now what is wrong, the check or the allocation result. I guess it will take some time only to

[Bug target/80211] ICE in curr_insn_transform, at lra-constraints.c:3816

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80211 --- Comment #1 from Vladimir Makarov --- I can not reproduce it. With the mentioned options I have warning: implicit declaration of function '__builtin_dfp_dtstsfi_ov'; did you mean '__builtin_fpclassify`? The option set has no sense for me

[Bug target/80148] [7 Regression] operand has impossible constraints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80148 --- Comment #6 from Vladimir Makarov --- Author: vmakarov Date: Fri Mar 24 18:47:38 2017 New Revision: 246467 URL: https://gcc.gnu.org/viewcvs?rev=246467=gcc=rev Log: 2017-03-24 Vladimir Makarov PR target/80148

[Bug target/80148] [7 Regression] operand has impossible constraints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80148 --- Comment #5 from Vladimir Makarov --- The fix proposed by Bernd for PR80160 does not solve the problem. So I am continuing to work on the patch.

[Bug rtl-optimization/80159] [7 regression] gcc takes very long time with -Os

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80159 --- Comment #3 from Vladimir Makarov --- Either patch proposed by Bernd for PR80160 or my patch on which I am working for PR80148 will solve the problem.

[Bug target/80160] [7 regression] operand has impossible constraints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80160 --- Comment #5 from Vladimir Makarov --- (In reply to Bernd Schmidt from comment #4) > Perhaps this. > > Index: lra-assigns.c > === > --- lra-assigns.c (revision 246226) > +++

[Bug target/80148] [7 Regression] operand has impossible constraints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80148 --- Comment #4 from Vladimir Makarov --- Thank you for reporting this. Something is wrong with processing insns for reloads. The asm-insn hash 2 the same operands mem[r263+12]. R263 is spilled for a reload. The mem becomes invalid and r263

[Bug target/80017] [5/6/7 Regression] ICE: Max. number of generated reload insns per insn is achieved (90)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80017 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Wed Mar 15 23:04:09 2017 New Revision: 246181 URL: https://gcc.gnu.org/viewcvs?rev=246181=gcc=rev Log: 2017-03-15 Vladimir Makarov PR target/80017

[Bug target/80017] [5/6/7 Regression] ICE: Max. number of generated reload insns per insn is achieved (90)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80017 --- Comment #1 from Vladimir Makarov --- Thank you for the report. I've reproduced and started to work on it. The fix will be probably ready on Wednesday.

[Bug rtl-optimization/79949] ICE in Max. number of generated reload insns per insn is achieved (90)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79949 --- Comment #5 from Vladimir Makarov --- Author: vmakarov Date: Thu Mar 9 14:43:17 2017 New Revision: 246003 URL: https://gcc.gnu.org/viewcvs?rev=246003=gcc=rev Log: 2017-03-09 Vladimir Makarov PR

[Bug rtl-optimization/79916] ICE in Max. number of generated reload insns per insn is achieved (90)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79916 --- Comment #6 from Vladimir Makarov --- I still can not reproduce it but I hope the fix for PR 79949 will be also a fix for this PR.

[Bug rtl-optimization/79949] ICE in Max. number of generated reload insns per insn is achieved (90)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79949 --- Comment #3 from Vladimir Makarov --- The fix will be ready tomorrow.

[Bug rtl-optimization/79949] ICE in Max. number of generated reload insns per insn is achieved (90)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79949 --- Comment #2 from Vladimir Makarov --- I've reproduced it and started to work on it.

[Bug rtl-optimization/79916] ICE in Max. number of generated reload insns per insn is achieved (90)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79916 --- Comment #1 from Vladimir Makarov --- Sorry, I can not reproduce the bug. I built a cross-compiler configured as --target=ppc64le-linux-gnu on today trunk.

[Bug rtl-optimization/79571] [5/6/7 Regression] ICE in Max. number of generated reload insns per insn is achieved (90)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79571 --- Comment #16 from Vladimir Makarov --- Author: vmakarov Date: Mon Mar 6 20:23:00 2017 New Revision: 245928 URL: https://gcc.gnu.org/viewcvs?rev=245928=gcc=rev Log: 2017-03-06 Vladimir Makarov PR

[Bug rtl-optimization/79571] [5/6/7 Regression] ICE in Max. number of generated reload insns per insn is achieved (90)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79571 --- Comment #15 from Vladimir Makarov --- My approach is to fix it in LRA by using a reload pass behaviour. We have (define_insn "*movti_internal" [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,v,v ,v ,m")

[Bug rtl-optimization/79571] [5/6/7 Regression] ICE in Max. number of generated reload insns per insn is achieved (90)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79571 --- Comment #7 from Vladimir Makarov --- I am working on the PR. I hope the fix will be ready at the beginning of the next week.

[Bug rtl-optimization/79779] [5/6/7 Regression] ICE on an invalid code with -fsanitize=undefined

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79779 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug target/69148] [5 Regression] ICE (floating point exception) on s390x-linux-gnu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69148 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/79456] [7 regression] Extra instruction emitted after LRA patch

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79456 --- Comment #1 from Vladimir Makarov --- I can not reproduce the bug on the fresh trunk any more. I believe the problem is analogous to https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79282 and it was solved last week.

[Bug target/79437] Redundant move instruction when getting sign bit of double on 32-bit architecture

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79437 --- Comment #3 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #2) > Even -mno-stv doesn't help here, the problem is that for the shift we don't > lower DImode operations here until too late (split2) and so EDX:EAX is used >

[Bug target/79636] [5/6/7 Regression] ICE in assign_by_spills, at lra-assigns.c:1457

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79636 --- Comment #2 from Vladimir Makarov --- The bug is also present in GCC-4.7 which uses the old reload pass. But GCC-4.4 works ok on the test. The culprit is in udivmod. GCC-4.4 generates a shift instead of udivmod generated by GCC-4.7 and the

[Bug target/79185] [5/6/7 Regression] register allocation in the addition of two 128 bit ints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79185 --- Comment #6 from Vladimir Makarov --- (In reply to Jeffrey A. Law from comment #5) > Is the CLOBBER even necessary anymore? Wasn't its only purpose to tell > dataflow that r88 was dead because our old flow analysis couldn't? > I guess the

[Bug target/79185] [5/6/7 Regression] register allocation in the addition of two 128 bit ints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79185 --- Comment #4 from Vladimir Makarov --- There are probably a lot of analogous problem reports. I'll try to put some analysis of the issue. Before IRA we have the following code: 2: r90:DI=di:DI REG_DEAD di:DI 3: r91:DI=si:DI

[Bug rtl-optimization/79541] lra reads uninitialized memory (with invalid input)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79541 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Fri Feb 17 16:10:59 2017 New Revision: 245536 URL: https://gcc.gnu.org/viewcvs?rev=245536=gcc=rev Log: 2017-02-17 Vladimir Makarov PR

[Bug rtl-optimization/78127] [5/6/7 Regression] AArch64 internal compiler error: in lra_eliminate, at lra-eliminations.c:1440

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78127 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Thu Feb 16 19:47:15 2017 New Revision: 245514 URL: https://gcc.gnu.org/viewcvs?rev=245514=gcc=rev Log: 2017-02-16 Vladimir Makarov PR

[Bug rtl-optimization/79541] lra reads uninitialized memory (with invalid input)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79541 --- Comment #2 from Vladimir Makarov --- The bug is not severe. It occurs only when wrong asm occurs. This asm is transformed into an USE and all its data is invalidated. If an insn is inserted before the USE we take a garbage as the offset

[Bug rtl-optimization/79541] lra reads uninitialized memory (with invalid input)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79541 --- Comment #1 from Vladimir Makarov --- Thank you, Bernd. I've reproduced the bug and started to work on it.

[Bug rtl-optimization/78127] [5/6/7 Regression] AArch64 internal compiler error: in lra_eliminate, at lra-eliminations.c:1440

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78127 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug target/79282] [7 Regresion] FAIL: gcc.target/arm/neon-for-64bits-1.c scan-assembler-times vshr 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79282 --- Comment #8 from Vladimir Makarov --- Author: vmakarov Date: Tue Feb 14 22:17:19 2017 New Revision: 245459 URL: https://gcc.gnu.org/viewcvs?rev=245459=gcc=rev Log: 2017-02-14 Vladimir Makarov PR target/79282

[Bug rtl-optimization/21182] [5/6/7 Regression] gcc can use registers but uses stack instead

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=21182 --- Comment #25 from Vladimir Makarov --- (In reply to Jeffrey A. Law from comment #24) > Do we happen to have easy access to the pressure at the various program > points? Dumping that with the points might prove fruitful in both the > search

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