[Bug rtl-optimization/60969] [4.9/4.10 Regression] ICE in output_129 in MMXMOV of mode MODE_SF for march=pentium4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60969 --- Comment #23 from Vladimir Makarov --- Author: vmakarov Date: Fri May 16 17:37:17 2014 New Revision: 210520 URL: http://gcc.gnu.org/viewcvs?rev=210520&root=gcc&view=rev Log: 2014-05-16 Vladimir Makarov PR rtl-optimization/60969 *

[Bug rtl-optimization/60969] [4.9/4.10 Regression] ICE in output_129 in MMXMOV of mode MODE_SF for march=pentium4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60969 --- Comment #22 from Vladimir Makarov --- Author: vmakarov Date: Fri May 16 17:21:04 2014 New Revision: 210519 URL: http://gcc.gnu.org/viewcvs?rev=210519&root=gcc&view=rev Log: 2014-05-16 Vladimir Makarov PR rtl-optimization/60969 *

[Bug rtl-optimization/60969] [4.9/4.10 Regression] ICE in output_129 in MMXMOV of mode MODE_SF for march=pentium4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60969 --- Comment #20 from Vladimir Makarov --- The problem is ira-costs.c. One pseudo gets equal costs for memory and all classes. Therefore when non-mmx hard regs are not enough, a mmx is used. After initialization of costs of reg classes for the

[Bug rtl-optimization/60769] [4.8 Regression] ICE: Max. number of generated reload insns per insn is achieved (90)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60769 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Thu Apr 10 23:22:10 2014 New Revision: 209285 URL: http://gcc.gnu.org/viewcvs?rev=209285&root=gcc&view=rev Log: 2014-04-10 Vladimir Makarov PR rtl-optimization/60769 * lr

[Bug rtl-optimization/60650] [ARM] LRA ICE in assign_by_spills

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60650 --- Comment #12 from Vladimir Makarov --- Author: vmakarov Date: Wed Apr 2 20:55:02 2014 New Revision: 209038 URL: http://gcc.gnu.org/viewcvs?rev=209038&root=gcc&view=rev Log: 2014-04-02 Vladimir Makarov PR rtl-optimization/60650 * l

[Bug rtl-optimization/60650] [ARM] LRA ICE in assign_by_spills

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60650 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug target/60697] [aarch64] LRA ICE (Segfault) while building 435.gromacs

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60697 --- Comment #4 from Vladimir Makarov --- Author: vmakarov Date: Fri Mar 28 22:14:36 2014 New Revision: 208926 URL: http://gcc.gnu.org/viewcvs?rev=208926&root=gcc&view=rev Log: 2014-03-28 Vladimir Makarov PR target/60697 * lra-constrai

[Bug target/60697] [aarch64] LRA ICE (Segfault) while building 435.gromacs

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60697 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug target/60675] [4.9 regression][aarch64] internal compiler error: Max. number of generated reload insns per insn is achieved (90)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60675 --- Comment #12 from Vladimir Makarov --- Author: vmakarov Date: Fri Mar 28 15:27:58 2014 New Revision: 208900 URL: http://gcc.gnu.org/viewcvs?rev=208900&root=gcc&view=rev Log: 2014-03-28 Vladimir Makarov PR target/60675 * lra-assigns

[Bug target/60675] [4.9 regression][aarch64] internal compiler error: Max. number of generated reload insns per insn is achieved (90)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60675 --- Comment #11 from Vladimir Makarov --- I've been working on it. I hope the patch will be ready today.

[Bug rtl-optimization/60650] [ARM] LRA ICE in assign_by_spills

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60650 --- Comment #4 from Vladimir Makarov --- Author: vmakarov Date: Thu Mar 27 18:49:44 2014 New Revision: 208876 URL: http://gcc.gnu.org/viewcvs?rev=208876&root=gcc&view=rev Log: 2014-03-27 Vladimir Makarov PR rtl-optimization/60650 * lr

[Bug rtl-optimization/60508] [4.8/4.9 Regression] internal compiler error: in lra_set_insn_recog_data, at lra.c:1082

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60508 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Fri Mar 14 16:34:57 2014 New Revision: 208570 URL: http://gcc.gnu.org/viewcvs?rev=208570&root=gcc&view=rev Log: 2014-03-14 Vladimir Makarov PR rtl-optimization/60508 * lr

[Bug rtl-optimization/57189] [4.9 Regression] Vector register is spilled for vector extract pattern

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189 --- Comment #8 from Vladimir Makarov --- Author: vmakarov Date: Thu Mar 13 15:52:50 2014 New Revision: 208549 URL: http://gcc.gnu.org/viewcvs?rev=208549&root=gcc&view=rev Log: 2014-03-13 Vladimir Makarov PR rtl-optimization/57189 * lr

[Bug rtl-optimization/60162] [4.9 Regression][lra] mlra appears to be using the FP registers for integer values and then moving on to GPR registers.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60162 --- Comment #4 from Vladimir Makarov --- (In reply to Ramana Radhakrishnan from comment #2) > Created attachment 32120 [details] > Reduced from gzip. > > Command line options. > > -march=armv7-a -mfpu=neon -mfloat-abi=hard -mthumb -O3 -mlra So

[Bug target/59222] [4.9 Regression] gcc.c-torture/compile/20050622-1.c ICEs at -O1 and above for aarch64-elf ILP32

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59222 --- Comment #5 from Vladimir Makarov --- Author: vmakarov Date: Thu Feb 27 17:06:02 2014 New Revision: 208201 URL: http://gcc.gnu.org/viewcvs?rev=208201&root=gcc&view=rev Log: 2014-02-27 Vladimir Makarov PR target/59222 * lra.c (lra_e

[Bug rtl-optimization/60317] [4.9 Regression] find_hard_regno_for compile time hog in libvpx

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60317 --- Comment #5 from Vladimir Makarov --- Author: vmakarov Date: Tue Feb 25 20:34:44 2014 New Revision: 208155 URL: http://gcc.gnu.org/viewcvs?rev=208155&root=gcc&view=rev Log: 2014-02-25 Vladimir Makarov PR rtl-optimization/60317 * pa

[Bug target/60298] [ARM/Thumb1] ICE caused by LRA for case pr54713-1.c

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60298 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Fri Feb 21 21:23:48 2014 New Revision: 208023 URL: http://gcc.gnu.org/viewcvs?rev=208023&root=gcc&view=rev Log: 2014-02-21 Vladimir Makarov PR target/60298 * lra-constrai

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 --- Comment #16 from Vladimir Makarov --- Author: vmakarov Date: Fri Feb 14 16:18:29 2014 New Revision: 207787 URL: http://gcc.gnu.org/viewcvs?rev=207787&root=gcc&view=rev Log: 2014-02-14 Vladimir Makarov Richard Earnshaw PR rtl

[Bug target/49008] A typo code found in genautomata.c

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49008 --- Comment #1 from Vladimir Makarov --- Author: vmakarov Date: Tue Feb 11 22:00:04 2014 New Revision: 207701 URL: http://gcc.gnu.org/viewcvs?rev=207701&root=gcc&view=rev Log: 2014-02-11 Vladimir Makarov PR target/49008 * genautomata.

[Bug rtl-optimization/60079] [LRA] ICE when compiling attached case.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60079 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug bootstrap/59913] [4.9 Regresion] bootstrap failure on arm-linux-gnueabihf

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59913 --- Comment #7 from Vladimir Makarov --- Author: vmakarov Date: Tue Feb 4 18:56:59 2014 New Revision: 207485 URL: http://gcc.gnu.org/viewcvs?rev=207485&root=gcc&view=rev Log: 2014-02-04 Vladimir Makarov PR bootstrap/59913 * lra-const

[Bug bootstrap/59985] stage2/3 compare error on lto-streamer-in.o

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59985 --- Comment #14 from Vladimir Makarov --- Author: vmakarov Date: Fri Jan 31 23:56:46 2014 New Revision: 207375 URL: http://gcc.gnu.org/viewcvs?rev=207375&root=gcc&view=rev Log: 2014-01-31 Vladimir Makarov PR bootstrap/59985 * lra-cons

[Bug rtl-optimization/59959] [4.9 Regression] LRA ICEs on a fortran case(Suspected to be similar to pr59915)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59959 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Thu Jan 30 21:15:51 2014 New Revision: 207323 URL: http://gcc.gnu.org/viewcvs?rev=207323&root=gcc&view=rev Log: 2014-01-30 Vladimir Makarov PR rtl-optimization/59959 * lr

[Bug bootstrap/59985] stage2/3 compare error on lto-streamer-in.o

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59985 --- Comment #12 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #11) > --- gcc/lra-constraints.c.jj 2014-01-24 16:27:35.0 +0100 > +++ gcc/lra-constraints.c 2014-01-30 18:10:03.795737809 +0100 > @@ -4049,7 +4049,7 @@

[Bug bootstrap/59913] [4.9 Regresion] bootstrap failure on arm-linux-gnueabihf

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59913 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/59915] [4.9 Regression] LRA ICE - Repeated looping over subreg reloads (gcc.c-torture/compile/simd-3.c)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59915 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Thu Jan 23 20:06:28 2014 New Revision: 207007 URL: http://gcc.gnu.org/viewcvs?rev=207007&root=gcc&view=rev Log: 2014-01-23 Vladimir Makarov PR regression/59915 * lra-cons

[Bug rtl-optimization/59477] [4.8/4.9 Regression] ICE: in assign_by_spills, at lra-assigns.c:1281 with -O

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59477 --- Comment #8 from Vladimir Makarov --- Author: vmakarov Date: Wed Jan 22 19:38:47 2014 New Revision: 206938 URL: http://gcc.gnu.org/viewcvs?rev=206938&root=gcc&view=rev Log: 2014-01-22 Vladimir Makarov PR rtl-optimization/59477 * lr

[Bug rtl-optimization/59896] [4.9 regression] Bootstrap: Thumb-1 LRA unable to generate reloads for jump_insn

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59896 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Tue Jan 21 21:26:33 2014 New Revision: 206908 URL: http://gcc.gnu.org/viewcvs?rev=206908&root=gcc&view=rev Log: 2014-01-21 Vladimir Makarov PR rtl-optimization/59896 * lr

[Bug rtl-optimization/59858] [4.8/4.9 Regression] ICE: assign_by_spills, at lra-assigns.c:1283

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59858 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Tue Jan 21 19:15:40 2014 New Revision: 206897 URL: http://gcc.gnu.org/viewcvs?rev=206897&root=gcc&view=rev Log: 2014-01-21 Vladimir Makarov PR rtl-optimization/59858 * lr

[Bug middle-end/59609] [4.9 Regression] LRA generates bad code for libgcc function udivmoddi4 on thumb1 target

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59609 --- Comment #5 from Vladimir Makarov --- Author: vmakarov Date: Thu Jan 16 19:13:54 2014 New Revision: 206677 URL: http://gcc.gnu.org/viewcvs?rev=206677&root=gcc&view=rev Log: 2014-01-16 Vladimir Makarov PR middle-end/59609 * lra-cons

[Bug rtl-optimization/59835] [4.9 Regression] gcc.target/i386/sse-2[34].c timeout

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59835 --- Comment #6 from Vladimir Makarov --- Author: vmakarov Date: Thu Jan 16 19:04:08 2014 New Revision: 206676 URL: http://gcc.gnu.org/viewcvs?rev=206676&root=gcc&view=rev Log: 2014-01-16 Vladimir Makarov PR rtl-optimization/59835 * ir

[Bug middle-end/59609] [4.9 Regression] LRA generates bad code for libgcc function udivmoddi4 on thumb1 target

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59609 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/59511] [4.9 Regression] FAIL: gcc.target/i386/pr36222-1.c scan-assembler-not movdqa with -mtune=corei7

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59511 --- Comment #4 from Vladimir Makarov --- Author: vmakarov Date: Wed Jan 15 17:32:47 2014 New Revision: 206636 URL: http://gcc.gnu.org/viewcvs?rev=206636&root=gcc&view=rev Log: 2014-01-15 Vladimir Makarov PR rtl-optimization/59511 * ir

[Bug target/59787] [ARM] mmx-2.c causes ICE when GCC is configured for cortex-a5/vfpv3-d16-fp16

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59787 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Tue Jan 14 19:07:01 2014 New Revision: 206605 URL: http://gcc.gnu.org/viewcvs?rev=206605&root=gcc&view=rev Log: 2014-01-14 Vladimir Makarov PR target/59787 * config/arm/a

[Bug rtl-optimization/56069] [4.7/4.8/4.9 Regression] RA pessimization

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56069 --- Comment #6 from Vladimir Makarov --- (In reply to Jeffrey A. Law from comment #5) > Maybe I'm missing something here. We have this immediately prior to IRA: > > ISTM that we want (reg 86) to prefer di and (reg 87) to prefer ax by way of > t

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 --- Comment #14 from Vladimir Makarov --- (In reply to Richard Earnshaw from comment #13) > When not optimizing for size, the register allocator should be able to use > the high registers as alternatives to spill slots (copy the value to a high >

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 --- Comment #10 from Vladimir Makarov --- ./cc1 -Os -mthumb -mcpu=arm7tdmi -fno-short-enums test.i -m{no-}lra -fno-schedule-insns2 original reload reload with change lra with change reg moves 104 86 101 al

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/59466] Slow code generation by LRA for memory addresses on PPC

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59466 Vladimir Makarov changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug rtl-optimization/59511] [4.9 Regression] FAIL: gcc.target/i386/pr36222-1.c scan-assembler-not movdqa with -mtune=corei7

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59511 --- Comment #3 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #2) > One movdqa started appearing with r204212, the second movdqa started > appearing with r204752. Vlad, can you please have a look? It seems the changes triggere

[Bug rtl-optimization/59466] Slow code generation by LRA for memory addresses on PPC

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59466 --- Comment #1 from Vladimir Makarov --- Author: vmakarov Date: Mon Dec 16 18:24:54 2013 New Revision: 206023 URL: http://gcc.gnu.org/viewcvs?rev=206023&root=gcc&view=rev Log: 2013-12-16 Vladimir Makarov PR rtl-optimization/59466 * em

[Bug rtl-optimization/59477] [4.8/4.9 Regression] ICE: in assign_by_spills, at lra-assigns.c:1281 with -O

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59477 --- Comment #2 from Vladimir Makarov --- Reload pass gives b.i: In function ‘void test1(_Bit_iterator)’: b.i:90:1: error: unable to find a register to spill in class ‘CREG’ } ^ b.i:90:1: error: this is the insn: (insn 29 43 30 2 (parallel [

[Bug middle-end/59470] [4.8 Regression] libstdc++ miscompilation after r205709

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59470 --- Comment #21 from Vladimir Makarov --- Author: vmakarov Date: Thu Dec 12 15:51:49 2013 New Revision: 205930 URL: http://gcc.gnu.org/viewcvs?rev=205930&root=gcc&view=rev Log: 2013-12-12 Vladimir Makarov PR middle-end/59470 * lra-coa

[Bug middle-end/59470] [4.8 Regression] libstdc++ miscompilation after r205709

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59470 --- Comment #20 from Vladimir Makarov --- Author: vmakarov Date: Thu Dec 12 15:48:23 2013 New Revision: 205929 URL: http://gcc.gnu.org/viewcvs?rev=205929&root=gcc&view=rev Log: 2013-12-12 Vladimir Makarov PR middle-end/59470 * lra-coa

[Bug middle-end/59470] [4.8 Regression] libstdc++ miscompilation after r205709

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59470 --- Comment #18 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #13) > Strange. From my limited testing, it does fix the regressions. I can fire > off now full scratch rpm builds with your patch. Sorry. My bad. I did not rebui

[Bug middle-end/59470] [4.8 Regression] libstdc++ miscompilation after r205709

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59470 --- Comment #12 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #9) > In -fdump-rtl-reload-slim we have incorrect: > >92: {sp:SI=sp:SI-0x30;clobber flags:CC;} >94: {dx:SI=sp:SI+0x2f;clobber flags:CC;} >95: NOTE_INSN

[Bug middle-end/59470] [4.8 Regression] libstdc++ miscompilation after r205709

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59470 --- Comment #11 from Vladimir Makarov --- Created attachment 31423 --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=31423&action=edit The patch fixing incorrect code generation

[Bug rtl-optimization/59466] New: Slow code generation by LRA for memory addresses on PPC

Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: vmakarov at gcc dot gnu.org Investigating SPEC2000 code (e.g. bzip2.c) generated by LRA on PPC using -O3 -mtune=power7 -mlra, sometimes I see code like addis 9,2,.LC77@toc@ha addi 9,9

[Bug rtl-optimization/59317] [4.9 Regression] [LRA,MIPS] ICE: in check_rtl, at lra.c (insn does not satisfy constraints)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59317 --- Comment #6 from Vladimir Makarov --- Author: vmakarov Date: Thu Dec 5 19:39:39 2013 New Revision: 205718 URL: http://gcc.gnu.org/viewcvs?rev=205718&root=gcc&view=rev Log: 2013-12-05 Vladimir Makarov PR rtl-optimization/59317 * lr

[Bug tree-optimization/57315] LTO and/or vectorizer performance regression on salsa20 core, 4.7->4.8

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57315 --- Comment #4 from Vladimir Makarov --- Zack, thanks for reporting this. Crypto algorithms are very interesting cases for RA. A lot of performance improvements were done for RA during gcc-4.9 development. Now on Intel Haswell I have bash-4.

[Bug rtl-optimization/59317] [4.9 Regression] [LRA,MIPS] ICE: in check_rtl, at lra.c (insn does not satisfy constraints)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59317 --- Comment #3 from Vladimir Makarov --- (In reply to Robert Suchanek from comment #2) > The latest patches do not seem to resolve the issue. > > Although the newly generated pseudos get ALL_REGS class assigned, the class > change does not happen

[Bug rtl-optimization/59086] [4.9 Regression] error: ‘asm’ operand has impossible constraints

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59086 --- Comment #9 from Vladimir Makarov --- (In reply to Jan Hubicka from comment #8) > > Do we have any documentation that states how many registers can be used in > > inline assembler for a particular arch and optset? "almost all" is not good > > e

[Bug rtl-optimization/59317] [4.9 Regression] [LRA,MIPS] ICE: in check_rtl, at lra.c (insn does not satisfy constraints)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59317 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/59340] [4.9 Regression] LRA enable-checking bootstrap failure since r205136

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59340 --- Comment #4 from Vladimir Makarov --- Andreas, could you check that the bootstrap is fixed. At least, the test is compiled by the cross-compiler.

[Bug rtl-optimization/59340] [4.9 Regression] LRA enable-checking bootstrap failure since r205136

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59340 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Fri Nov 29 20:08:38 2013 New Revision: 205541 URL: http://gcc.gnu.org/viewcvs?rev=205541&root=gcc&view=rev Log: 2013-11-29 Vladimir Makarov PR rtl-optimization/59340 * lr

[Bug rtl-optimization/59340] [4.9 Regression] LRA enable-checking bootstrap failure since r205136

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59340 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug target/57293] [4.8/4.9 Regression] not needed frame pointers on IA-32 (performance regression?)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57293 --- Comment #9 from Vladimir Makarov --- Author: vmakarov Date: Thu Nov 28 21:45:21 2013 New Revision: 205498 URL: http://gcc.gnu.org/viewcvs?rev=205498&root=gcc&view=rev Log: 2013-11-28 Vladimir Makarov PR target/57293 * ira.h (ira_s

[Bug rtl-optimization/57410] [4.9 Regression] ICE: in emit_spill_move, at lra-constraints.c:863 with -fpeel-loops and uninitialised variable

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57410 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Wed Nov 27 16:30:48 2013 New Revision: 205451 URL: http://gcc.gnu.org/viewcvs?rev=205451&root=gcc&view=rev Log: 2013-11-27 Vladimir Makarov PR rtl-optimization/57410 * gc

[Bug rtl-optimization/56339] [4.8/4.9 Regression]: Suboptimal register allocation

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56339 --- Comment #16 from Vladimir Makarov --- The problem was fixed by the patch removing regmove and improving hardware reg preferences in IRA.

[Bug target/57293] [4.8/4.9 Regression] not needed frame pointers on IA-32 (performance regression?)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57293 --- Comment #8 from Vladimir Makarov --- Sorry, ignore my previous comment. It should be for PR56339.

[Bug target/57293] [4.8/4.9 Regression] not needed frame pointers on IA-32 (performance regression?)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57293 --- Comment #7 from Vladimir Makarov --- The problem was fixed by a patch removing regmove and improving hardware preferences in IRA.

[Bug rtl-optimization/59086] [4.9 Regression] error: ‘asm’ operand has impossible constraints

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59086 --- Comment #3 from Vladimir Makarov --- First of all, reload also cannot generate this code with mentioned i386.c change When we use -maccumulate-outgoing-args, we have before reload/LRA (insn 6 10 7 2 (parallel [ (set (reg:SI 87 [

[Bug rtl-optimization/59133] [4.9 regression] ICE after r204219 on SPEC2006 435.gromacs.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59133 --- Comment #4 from Vladimir Makarov --- Author: vmakarov Date: Wed Nov 20 20:32:57 2013 New Revision: 205141 URL: http://gcc.gnu.org/viewcvs?rev=205141&root=gcc&view=rev Log: 2013-11-20 Vladimir Makarov PR rtl-optimization/59133 * lr

[Bug rtl-optimization/59086] [4.9 Regression] error: ‘asm’ operand has impossible constraints

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59086 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/59133] [4.9 regression] ICE after r204219 on SPEC2006 435.gromacs.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59133 --- Comment #3 from Vladimir Makarov --- I've started to work on it. The problem is in that LRA has not enough code to deal with creation of pseudos out of its scope. I guess the fix will be ready next week on Wednesday as the patch will need a

[Bug rtl-optimization/59036] [4.9 regression] Performance degradation after r204212 on 32-bit x86 targets.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59036 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Wed Nov 13 18:00:43 2013 New Revision: 204752 URL: http://gcc.gnu.org/viewcvs?rev=204752&root=gcc&view=rev Log: 2013-11-13 Vladimir Makarov PR rtl-optimization/59036 * ir

[Bug other/58712] [4.9 Regression] issues found by --enable-checking=valgrind

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58712 --- Comment #9 from Vladimir Makarov --- Author: vmakarov Date: Tue Nov 12 21:33:06 2013 New Revision: 204720 URL: http://gcc.gnu.org/viewcvs?rev=204720&root=gcc&view=rev Log: 2013-11-12 Vladimir Makarov PR other/58712 * ira-costs.c (

[Bug rtl-optimization/59036] [4.9 regression] Performance degradation after r204212 on 32-bit x86 targets.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59036 --- Comment #2 from Vladimir Makarov --- (In reply to Yuri Rumyantsev from comment #0) > After patch to improve register preferencing in IRA and to *remove regmove* > pass we noticed performance degradation on several benchmarks from eembc2.0 > su

[Bug rtl-optimization/58967] Powerpc -mlra cannot compile quadrature_lib.cc in Spec2006 with -O3 -ffast-math -funroll-loops -m32

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58967 --- Comment #1 from Vladimir Makarov --- Author: vmakarov Date: Mon Nov 4 21:09:12 2013 New Revision: 204365 URL: http://gcc.gnu.org/viewcvs?rev=204365&root=gcc&view=rev Log: 2013-11-04 Vladimir Makarov PR rtl-optimization/58967 * co

[Bug rtl-optimization/58968] Powerpc -mlra cannot compile ormas1.f in gamess Spec 2006 with -m32 -mcpu=power7 -O3 -mlra -w -ffast-math -funroll-loops

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58968 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/58968] Powerpc -mlra cannot compile ormas1.f in gamess Spec 2006 with -m32 -mcpu=power7 -O3 -mlra -w -ffast-math -funroll-loops

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58968 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Mon Nov 4 16:12:29 2013 New Revision: 204353 URL: http://gcc.gnu.org/viewcvs?rev=204353&root=gcc&view=rev Log: 2013-11-04 Vladimir Makarov PR rtl-optimization/58968 * lr

[Bug bootstrap/58933] IRA ICE in update_costs_from_allocno

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58933 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Thu Oct 31 03:14:07 2013 New Revision: 204245 URL: http://gcc.gnu.org/viewcvs?rev=204245&root=gcc&view=rev Log: 2013-10-30 Vladimir Makarov PR bootstrap/58933 * ira-color

[Bug rtl-optimization/57410] [4.9 Regression] ICE: in emit_spill_move, at lra-constraints.c:863 with -fpeel-loops and uninitialised variable

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57410 --- Comment #1 from Vladimir Makarov --- I can not reproduce it on today trunk. I guess it was fixed by some LRA patch but I ca not say by what patch exactly as there were too many LRA patches since May.

[Bug target/58784] [ARM] LRA legitimate address issue with misalign neon_store

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58784 --- Comment #1 from Vladimir Makarov --- Author: vmakarov Date: Wed Oct 30 15:04:39 2013 New Revision: 204215 URL: http://gcc.gnu.org/viewcvs?rev=204215&root=gcc&view=rev Log: 2013-10-30 Vladimir Makarov PR target/58784 * lra.c (check

[Bug rtl-optimization/58826] [4.9 Regression] Runfail on CPU2006 436.cactusADM with after r203377 for core-avx2 target.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58826 --- Comment #4 from Vladimir Makarov --- (In reply to Yuri Rumyantsev from comment #2) > In fact LRA is responsible for this failure - there is a bug in constant > regeneration. LRA correctly regenerates all occurrences of virtual register > which

[Bug rtl-optimization/58759] [4.9 Regression] wrong code (segfaults) at -O2 on x86_64-linux-gnu in 32-bit mode

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58759 --- Comment #7 from Vladimir Makarov --- Author: vmakarov Date: Fri Oct 25 21:34:26 2013 New Revision: 204080 URL: http://gcc.gnu.org/viewcvs?rev=204080&root=gcc&view=rev Log: 2013-10-25 Vladimir Makarov PR rtl-optimization/58759 * lr

[Bug rtl-optimization/58759] [4.9 Regression] wrong code (segfaults) at -O2 on x86_64-linux-gnu in 32-bit mode

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58759 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/58438] [4.9 Regression] ICE: in check_rtl, at lra.c:2036

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58438 --- Comment #5 from Vladimir Makarov --- Author: vmakarov Date: Wed Sep 18 18:24:49 2013 New Revision: 202714 URL: http://gcc.gnu.org/viewcvs?rev=202714&root=gcc&view=rev Log: 2013-09-18 Vladimir Makarov PR rtl-optimization/58438 * lr

[Bug middle-end/58418] [4.9 Regression] wrong code at -O2 and -O3 on x86_64-linux-gnu (in 32-bit mode)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58418 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Mon Sep 16 15:12:22 2013 New Revision: 202630 URL: http://gcc.gnu.org/viewcvs?rev=202630&root=gcc&view=rev Log: 2013-09-16 Vladimir Makarov PR middle-end/58418 * lra-cons

[Bug middle-end/58335] S/390: reload vs lra regression - testcase builtin-in-setjmp

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58335 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Thu Sep 12 18:23:09 2013 New Revision: 202536 URL: http://gcc.gnu.org/viewcvs?rev=202536&root=gcc&view=rev Log: 2013-09-12 Vladimir Makarov PR middle-end/58335 * lra-elim

[Bug middle-end/58335] S/390: reload vs lra regression - testcase builtin-in-setjmp

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58335 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/57459] [4.8 Regression] LRA inheritance bug

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57459 --- Comment #9 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #8) > Created attachment 30643 [details] > rh995446.i > > We've got this reported in > https://bugzilla.redhat.com/show_bug.cgi?id=995446 too. > I've created a self-

[Bug rtl-optimization/57963] LRA S/390: esa mode failure memcpy-chk

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57963 --- Comment #1 from Vladimir Makarov --- Thanks, Andreas. I've reproduced the bug. I hope to fix it on this week.

[Bug rtl-optimization/57676] [4.8/4.9 Regression] ICE: Maximum number of LRA constraint passes is achieved (30)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57676 --- Comment #2 from Vladimir Makarov --- That is a pretty interesting test case. Roughly speaking, we have chains of divmodsi4 insns: p1 / p2 ... p3 / p1 P1 (and many others) gets AX. But it is necessary for P3 in the second insn. So on each

[Bug rtl-optimization/57447] [4.9 Regression] ICE on 435.gromacs from spec2006 after r199298

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57447 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/55342] [4.8/4.9 Regression] [LRA,x86] Non-optimal code for simple loop with LRA

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55342 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/57468] [4.9 Regression] 26% performance drop on important benchmark after r199298.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57468 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug middle-end/56461] [4.8 Regression] GCC is leaking lots of memory

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56461 --- Comment #5 from Vladimir Makarov 2013-02-26 20:45:57 UTC --- (In reply to comment #4) > Created attachment 29544 [details] > gcc48-pr56461-2.patch > Sorry, I should have checked on leaks when I submitted LRA first time. The patch

[Bug inline-asm/56148] [4.8 Regression] inline asm matching constraint with different mode

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56148 --- Comment #15 from Vladimir Makarov 2013-02-22 16:30:33 UTC --- Author: vmakarov Date: Fri Feb 22 16:30:22 2013 New Revision: 196223 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=196223 Log: 2013-02-22 Vladimir Makarov

[Bug rtl-optimization/56348] internal compiler error in assign_by_spills with -m32 -fPIC -msse2

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56348 Vladimir Makarov changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|

[Bug rtl-optimization/56348] internal compiler error in assign_by_spills with -m32 -fPIC -msse2

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56348 --- Comment #2 from Vladimir Makarov 2013-02-15 19:17:16 UTC --- Author: vmakarov Date: Fri Feb 15 19:17:02 2013 New Revision: 196090 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=196090 Log: 2013-02-15 Vladimir Makarov

[Bug rtl-optimization/56348] internal compiler error in assign_by_spills with -m32 -fPIC -msse2

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56348 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/56339] [4.8 Regression]: Suboptimal register allocation

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56339 --- Comment #5 from Vladimir Makarov 2013-02-15 16:48:19 UTC --- (In reply to comment #4) > Perhaps for regmove IRA classes should be set up unconditionally: > > Index: regmove.c > ===

[Bug target/56184] [4.8 Regression] Internal compiler error in push_reload during bootstrap stage 2

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56184 --- Comment #8 from Vladimir Makarov 2013-02-13 17:40:33 UTC --- Author: vmakarov Date: Wed Feb 13 17:40:22 2013 New Revision: 196019 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=196019 Log: 2013-02-13 Vladimir Makarov

[Bug target/56184] [4.8 Regression] Internal compiler error in push_reload during bootstrap stage 2

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56184 --- Comment #7 from Vladimir Makarov 2013-02-13 15:15:14 UTC --- (In reply to comment #6) > > Unfortunately I'm not really familiar with the live range splitting code; > maybe > Vladimir can help with this? Yes, Ulrich. I've started

[Bug inline-asm/56148] [4.8 Regression] inline asm matching constraint with different mode

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56148 --- Comment #8 from Vladimir Makarov 2013-02-12 17:44:56 UTC --- Author: vmakarov Date: Tue Feb 12 17:44:47 2013 New Revision: 195988 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=195988 Log: 2013-02-12 Vladimir Makarov

[Bug rtl-optimization/56246] [4.8 regression] ICE in assign_by_spills, at lra-assigns.c:1262

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56246 --- Comment #3 from Vladimir Makarov 2013-02-08 21:59:16 UTC --- Author: vmakarov Date: Fri Feb 8 21:59:11 2013 New Revision: 195902 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=195902 Log: 2013-02-08 Vladimir Makarov

[Bug rtl-optimization/56246] [4.8 regression] ICE in assign_by_spills, at lra-assigns.c:1262

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56246 --- Comment #2 from Vladimir Makarov 2013-02-08 16:39:37 UTC --- (In reply to comment #1) > -m32 -march=i686 -mtune=generic -O2 -fno-omit-frame-pointer -fpic > needed for me. > Regressed with LRA merge. I'll be working on it.

[Bug rtl-optimization/56225] [4.8 Regression] ICE in lra-constraints.c when executing the testsuite with -m32 -march=pentium3

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56225 --- Comment #2 from Vladimir Makarov 2013-02-07 17:15:30 UTC --- Author: vmakarov Date: Thu Feb 7 17:15:02 2013 New Revision: 195856 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=195856 Log: 2013-02-07 Vladimir Makarov

[Bug middle-end/55889] [4.8 Regression] ICE: in move_op_ascend, at sel-sched.c:6153 with -fschedule-insns -fselective-scheduling

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55889 --- Comment #27 from Vladimir Makarov 2013-02-06 21:36:59 UTC --- (In reply to comment #26) > You are right, your suggestions is what I sketched in comment #21 as choices 1 > or 2. Sorry for my unclear expalanation of what was actually ha

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