https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90181
--- Comment #7 from Segher Boessenkool ---
(In reply to nfxjfg from comment #6)
> Yes, it's clear that that the constraint can't be _just_ the register name,
> since they'll clash with builtin constraints now or with future
> architectures
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90181
--- Comment #6 from nfxjfg at googlemail dot com ---
Yes, it's clear that that the constraint can't be _just_ the register name,
since they'll clash with builtin constraints now or with future architectures
(which may add arbitrary register
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90181
--- Comment #5 from Andrew Pinski ---
Actually it is not as bad if you use preprocessor tricks.
Like this code from glibc for aarch64:
# undef INTERNAL_SYSCALL_RAW
# define INTERNAL_SYSCALL_RAW(name, err, nr, args...) \
({ long
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90181
Segher Boessenkool changed:
What|Removed |Added
Status|RESOLVED|REOPENED
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90181
--- Comment #3 from nfxjfg at googlemail dot com ---
Yes, it's documented this way, but it makes it appear all kinds of fragile. For
one, I normally expect that the compiler will reorder and interleave any
statements in my code (because that's
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90181
Andrew Pinski changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90181
--- Comment #1 from Andreas Schwab ---
x86 doesn't support this either. It just happens to have a few register
classes that consist of a single register, but only because of ISA constraints.
