http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60162
Bug ID: 60162 Summary: [4.9 lra regression] mlra appears to be using the FP registers as a set of spill registers for ARM. Product: gcc Version: 4.9.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: ramana at gcc dot gnu.org This is something that I've just noticed with spec2k gzip : longest_match. If the function is compiled for a cross arm-none-linux-gnueabihf toolchain with the following parameters, --with-arch=armv7-a --with-fpu=neon --with-float=hard With a cross toolchain using mlra by default I get code that loads a value into an FP register and then moves this over to an integer register. While this is not that big a problem on some of the newer cores, it will be an issue on older cores where the latency of such transfers can be pretty high. You can experiment with -mno-lra to see the difference in code generated and this is essentially something that has shown up rather recently. Bisecting and will follow up in the morning with a testcase.