[Bug middle-end/79209] [5/6/7 Regression] AArch64: Inconsistent packed volatile bitfield accesses

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79209 --- Comment #5 from Pekka S --- It's true what you quoted, but on the other hand the current behaviour does not produce code that will not fault -- it will indeed fault. I see the rationale behind the packed

[Bug middle-end/79209] [5/6/7 Regression] AArch64: Inconsistent packed volatile bitfield accesses

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79209 Jakub Jelinek changed: What|Removed |Added CC||jakub at gcc dot gnu.org --- Comment #4

[Bug middle-end/79209] [5/6/7 Regression] AArch64: Inconsistent packed volatile bitfield accesses

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79209 --- Comment #3 from Richard Biener --- On x86_64 expansion is fine: ;; MEM[(volatile struct s0_t *)4B].y ={v} 1; (insn 5 4 6 (set (reg/f:DI 89) (const_int 4 [0x4])) "t.c":58 -1 (nil)) (insn 6 5 8 (set (reg:SI 90)

[Bug middle-end/79209] [5/6/7 Regression] AArch64: Inconsistent packed volatile bitfield accesses

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79209 Richard Biener changed: What|Removed |Added Target|aarch64 |aarch64, x86_64-*-*