[Bug rtl-optimization/108826] Inefficient address generation on POWER and RISC-V

2023-09-28 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108826 Andrew Pinski changed: What|Removed |Added CC||lis8215 at gmail dot com --- Comment

[Bug rtl-optimization/108826] Inefficient address generation on POWER and RISC-V

2023-02-16 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108826 --- Comment #6 from Andrew Pinski --- (In reply to palmer from comment #5) > We've run into a handful of things that look like this before, I'm not sure > if it's a backend issue or something more general. There's two patterns > here that are

[Bug rtl-optimization/108826] Inefficient address generation on POWER and RISC-V

2023-02-16 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108826 --- Comment #5 from palmer at gcc dot gnu.org --- We've run into a handful of things that look like this before, I'm not sure if it's a backend issue or something more general. There's two patterns here that are frequently bad on RISC-V:

[Bug rtl-optimization/108826] Inefficient address generation on POWER and RISC-V

2023-02-16 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108826 Andrew Pinski changed: What|Removed |Added Keywords||missed-optimization Last

[Bug rtl-optimization/108826] Inefficient address generation on POWER and RISC-V

2023-02-16 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108826 --- Comment #3 from Andrew Pinski --- (In reply to Andrew Pinski from comment #2) > Note I need to better understand why the C++ front-end thinks this would be > invalid ... Oh because the struct name is unnamed :).

[Bug rtl-optimization/108826] Inefficient address generation on POWER and RISC-V

2023-02-16 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108826 --- Comment #2 from Andrew Pinski --- Actually this is aarch64: ldr x1, [x0, #:lo12:.LANCHOR0] ldr w0, [x3, 8] and w0, w2, w0, lsr 6 add x0, x0, 200 ldr w0, [x1, x0, lsl 2] str

[Bug rtl-optimization/108826] Inefficient address generation on POWER and RISC-V

2023-02-16 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108826 --- Comment #1 from Andrew Pinski --- AARCH64 looks ok too because of the use of more complex adddresses: ldr w0, [x0, #:lo12:.LANCHOR0] and w0, w2, w0, lsr 6 add x0, x0, 200 ldr w0, [x1, x0, lsl