https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112474
Bug ID: 112474
Summary: MIPS: missed optimization for assigning HI reg to zero
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: lis8215 at gmail dot com
Target Milestone: ---
Created attachment 56550
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56550&action=edit
the patch
At the moment GCC emits move $0 to a GPR register and then move to HI (mthi)
from that register as part of DI/TI MADD operation.
It is feasible to avoid such copying when intermediate register isn't used
anymore and reword RTL to emit only `mthi $0`.
So the following output:
...
move $3, $0
mthi $3
; reg dead $3
...
Can be simply reworded as:
...
move $3, $0 ; << will be removed by DCE later
mthi $0
...
Silly patch, which doing such optimization, provided.
Thanks.
