https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115261
Bug ID: 115261
Summary: FAIL: gcc.target/s390/vector/vec-abi-vararg-1.c
Product: gcc
Version: unknown
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: stefansf at gcc dot gnu.org
Target Milestone: ---
Target: s390*-*-*
After r11-5821-gebdfd1606da6b5 multiple BIT_INSERT_EXPRs are vectorized which
as a side-effect leads to the usage of V2SI which seems to be the culprit of an
extra stack slot. For s390/vector/vec-abi-vararg-1.c we end up with
(insn 11 10 12 2 (set (subreg:V2SI (reg:V4SI 73 [ _3 ]) 0)
(plus:V2SI (mem:V2SI (plus:DI (reg/f:DI 32 %ap)
(const_int 16 [0x10])) [0 MEM[(v2si * {ref-all})_26 +
16B]+0 S8 A64])
(mem:V2SI (plus:DI (reg/f:DI 32 %ap)
(const_int 40 [0x28])) [0 MEM[(v2si * {ref-all})_26 +
40B]+0 S8 A64]))) "vec-abi-vararg-1.c":44:16 581 {addv2si3}
(nil))
which reload needs to fix
11: r79:V2SI=r80:V2SI+r81:V2SI
Inserting insn reload before:
26: r80:V2SI=[%ap:DI+0x170]
27: r81:V2SI=[%ap:DI+0x188]
Inserting insn reload after:
25: r73:V4SI#0=r79:V2SI
...
12: r74:V2DI=sign_extend(vec_select(r82:V4SI,parallel))
REG_DEAD r73:V4SI
Inserting insn reload before:
28: r82:V4SI=r73:V4SI
which materializes as:
(insn 10 14 24 2 (set (reg:V4SI 16 %f0 [orig:73 _3 ] [73])
(const_vector:V4SI [
(const_int 0 [0]) repeated x4
])) "vec-abi-vararg-1.c":44:16 410 {movv4si}
(expr_list:REG_EQUAL (const_vector:V4SI [
(const_int 0 [0]) repeated x4
])
(nil)))
(insn 24 10 26 2 (set (mem/c:V4SI (plus:DI (reg/f:DI 15 %r15)
(const_int 160 [0xa0])) [4 %sfp+-48 S16 A64])
(reg:V4SI 16 %f0 [orig:73 _3 ] [73])) "vec-abi-vararg-1.c":44:16 410
{movv4si}
(nil))
(insn 26 24 27 2 (set (reg:V2SI 16 %f0 [80])
(mem:V2SI (plus:DI (reg/f:DI 15 %r15)
(const_int 384 [0x180])) [0 MEM[(v2si * {ref-all})_26 + 16B]+0
S8 A64])) "vec-abi-vararg-1.c":44:16 426 {movv2si}
(nil))
(insn 27 26 11 2 (set (reg:V2SI 17 %f2 [81])
(mem:V2SI (plus:DI (reg/f:DI 15 %r15)
(const_int 408 [0x198])) [0 MEM[(v2si * {ref-all})_26 + 40B]+0
S8 A64])) "vec-abi-vararg-1.c":44:16 426 {movv2si}
(nil))
(insn 11 27 25 2 (set (reg:V2SI 16 %f0 [79])
(plus:V2SI (reg:V2SI 16 %f0 [80])
(reg:V2SI 17 %f2 [81]))) "vec-abi-vararg-1.c":44:16 581 {addv2si3}
(nil))
(insn 25 11 28 2 (set (mem/c:V2SI (plus:DI (reg/f:DI 15 %r15)
(const_int 160 [0xa0])) [4 %sfp+-48 S8 A64])
(reg:V2SI 16 %f0 [79])) "vec-abi-vararg-1.c":44:16 426 {movv2si}
(nil))
(insn 28 25 12 2 (set (reg:V4SI 16 %f0 [orig:73 _3 ] [73])
(mem/c:V4SI (plus:DI (reg/f:DI 15 %r15)
(const_int 160 [0xa0])) [4 %sfp+-48 S16 A64]))
"vec-abi-vararg-1.c":44:16 410 {movv4si}
(nil))
(insn 12 28 29 2 (set (reg:V2DI 16 %f0 [orig:74 _29 ] [74])
(sign_extend:V2DI (vec_select:V2SI (reg:V4SI 16 %f0 [orig:73 _3 ] [73])
(parallel [
(const_int 0 [0])
(const_int 1 [0x1])
])))) "vec-abi-vararg-1.c":44:16 1345 {vec_unpacks_hi_v4si}
(nil))
Insn 25 and 28 convert a V2SI into a V4SI via stack. It is a bit unfortunate
since the resulting V4SI vector is used for unpacking which ignores the
rightmost half, i.e., zeroing out the rightmost half by going over the stack is
unnecessary.
