[Bug rtl-optimization/70164] [6 Regression] Code/performance regression due to poor register allocation on Cortex-M0

2016-03-24 Thread law at redhat dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164 --- Comment #14 from Jeffrey A. Law --- Some further notes. I was looking at what the impact would be if we just stopped recording the problematical equivalences in CSE, both to see if the equivalences are useful at all, and if they are, to get

[Bug rtl-optimization/70164] [6 Regression] Code/performance regression due to poor register allocation on Cortex-M0

2016-03-23 Thread law at redhat dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164 Jeffrey A. Law changed: What|Removed |Added Priority|P1 |P2 --- Comment #13 from Jeffrey A. Law

[Bug rtl-optimization/70164] [6 Regression] Code/performance regression due to poor register allocation on Cortex-M0

2016-03-23 Thread law at redhat dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164 --- Comment #11 from Jeffrey A. Law --- So given the conflicts during IRA I can't see a way for IRA to do a better job. Essentially the key allocno/pseudo wants hard reg 0 to avoid the spillage, but it also conflicts with hard reg 0. Prior to C

[Bug rtl-optimization/70164] [6 Regression] Code/performance regression due to poor register allocation on Cortex-M0

2016-03-23 Thread law at redhat dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164 --- Comment #12 from Jeffrey A. Law --- Slight correction. I was looking at the wrong part of the dump when I said cse1 didn't change insn 28. It is cse1 that changes insn 28. So this is strictly an issue with the transformations cse1 makes.

[Bug rtl-optimization/70164] [6 Regression] Code/performance regression due to poor register allocation on Cortex-M0

2016-03-23 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164 --- Comment #10 from Vladimir Makarov --- (In reply to Jeffrey A. Law from comment #9) > I think that's a fair characterization. The extra copy emitted by the older > compiler gives the allocator more freedom. With coalescing getting more > ag

[Bug rtl-optimization/70164] [6 Regression] Code/performance regression due to poor register allocation on Cortex-M0

2016-03-23 Thread law at redhat dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164 --- Comment #9 from Jeffrey A. Law --- I think that's a fair characterization. The extra copy emitted by the older compiler gives the allocator more freedom. With coalescing getting more aggressive, the copy is gone and the allocator's freedom

[Bug rtl-optimization/70164] [6 Regression] Code/performance regression due to poor register allocation on Cortex-M0

2016-03-23 Thread rguenth at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164 Richard Biener changed: What|Removed |Added Keywords||missed-optimization, ra Prior

[Bug rtl-optimization/70164] [6 Regression] Code/performance regression due to poor register allocation on Cortex-M0

2016-03-10 Thread law at redhat dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug rtl-optimization/70164] [6 Regression] Code/performance regression due to poor register allocation on Cortex-M0

2016-03-10 Thread rguenth at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164 Richard Biener changed: What|Removed |Added CC||law at gcc dot gnu.org,