https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102218
Bug ID: 102218 Summary: 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm Product: gcc Version: 9.0 Status: UNCONFIRMED Keywords: wrong-code Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: tnfchris at gcc dot gnu.org Target Milestone: --- AArch64 and Arm libatomic do no support 128-bit atomics and so use the pthreads fallback code on atomic operations. The fallback code for atomic compare and exchange does the following pre_seq_barrier (smodel); magic = protect_start (mptr); and for correctness relies on the target implementing pre_seq_barrier. AArch64 and Arm however do not provide an implementation or pre_seq_barrier and post_seq_barrier and the default implementations are just empty functions: static inline void __attribute__((always_inline, artificial)) pre_seq_barrier(int model) { } However for correctness on __ATOMIC_SEQ_CST a barrier needs to be emitted here which isn't happening on any GCC version.